Simulator Configuration Guide for Synopsys Models

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Appendix B: Using Custom Memory ModelsSimulator Configuration Guide7. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v Verilog_modules custom_model_files \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchUsing Custom Memory Models with MTIVerilogCustom memory models work with MTI Verilog (ModelSim) using a PLI applicationcalled LMTV that is delivered in the form of a swiftpli_mti shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in the following example:% vlib work% vmap work workThis step also produces a modelsim.ini file.3. Edit the modelsim.ini file to add a resolution statement as shown in the followingexample:Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using SmartModels with ModelSim Verilog” onpage 61).4. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.290 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory Models5. Instantiate your custom memory models in your design. Define ports andparameters as required. For details, see “Instantiating Custom Memory Models” onpage 285. For information on message levels and message level constants, see“Controlling Messages” on page 283.6. Define the working directory that contains your testbench.% vlib work_dir7. Compile your code as shown in the following examples:% vlog -work work_dir testbench.v Verilog_modules custom_model_files\+incdir+$LMC_HOME/sim/pli/src8. Invoke the simulator as shown in the following examples:❍❍❍HP-UX:% vsim -pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl \-c work_dir.testbenchSolaris:% vsim -pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so \-c work_dir.testbenchLinux:% vsim -pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so \-c work_dir.testbenchNoteIf you are also using SmartModels, FlexModels, or DesignWare MemoryModels in your design, you do not need to load the swiftpl_mti again, sincethe same library is used to enable all three types of models in MTI-Verilog.October 6, 2003 Synopsys, Inc. 291
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Simulator ConfigurationGuide for Sy
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Page 268 and 269: Appendix A: Using LMTV with Synopsy
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Simulator Configuration Guide for Synopsys Models

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