Simulator Configuration Guide for Synopsys Models

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide7. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v Verilog_modules custom_model_files \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchUsing Custom Memory Models with MTIVerilogCustom memory models work with MTI Verilog (ModelSim) using a PLI applicationcalled LMTV that is delivered in the form of a swiftpli_mti shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in the following example:% vlib work% vmap work workThis step also produces a modelsim.ini file.3. Edit the modelsim.ini file to add a resolution statement as shown in the followingexample:Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using SmartModels with ModelSim Verilog” onpage 61).4. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.290 Synopsys, Inc. October 6, 2003