Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsUsing Custom Memory Models withNC-VerilogCustom memory models work with NC-Verilog using a PLI application called LMTVthat is delivered in the form of a swiftpli shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.3. Instantiate your custom memory models in your design. Define ports andparameters as required. For information on parameters used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.4. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.5. Invoke the NC-Verilog simulator to compile and simulate your design as shown inthe example below:% ncverilog testbench Verilog_modules custom_model_files \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w6. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.❍❍Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.varOctober 6, 2003 Synopsys, Inc. 289