Simulator Configuration Guide for Synopsys Models

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Appendix B: Using Custom Memory ModelsSimulator Configuration Guide❍❍If you are using the MemScope Dynamic Data Exchange (DDX) feature:% vcs Verilog_modules custom_model_files \-Xstrict=0x01 -syslib “-lpthread” \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/srcHP-UX:Linux:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/hp700.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/src \% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/x86_linux.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/src \-LDFLAGS -rdynamic7. Invoke VCS and simulate your design:% simvVCS Custom Memory Model ExplanationTable 40 lists and explains each line in the invocation examples above.Table 40: VCS Custom Memory Model ExplanationLine Reference$VCS_HOME/bin/vcscustom_model.v custom_model_tb.vDescriptionPath to the file that starts the VCS simulator,followed by the specified model andtestbench Verilog files.-P $LMC_HOME/sim/pli/src/slm_pli.tab Specifies the PLI table entry file.$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o-Mupdate-LDFLAGS switchesSpecifies the platform-specific PLI objectfile.This specifies incremental compilation,which causes VCS to compile only themodules that have changed since the last run.Additional platform-specific switches thatmay be needed.288 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory ModelsUsing Custom Memory Models withNC-VerilogCustom memory models work with NC-Verilog using a PLI application called LMTVthat is delivered in the form of a swiftpli shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.3. Instantiate your custom memory models in your design. Define ports andparameters as required. For information on parameters used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.4. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.5. Invoke the NC-Verilog simulator to compile and simulate your design as shown inthe example below:% ncverilog testbench Verilog_modules custom_model_files \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w6. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.❍❍Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.varOctober 6, 2003 Synopsys, Inc. 289
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Simulator ConfigurationGuide for Sy
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Page 268 and 269: Appendix A: Using LMTV with Synopsy
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Simulator Configuration Guide for Synopsys Models

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