Simulator Configuration Guide for Synopsys Models

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Appendix B: Using Custom Memory ModelsSimulator Configuration GuideControlling Message OutputThere are three ways to control messaging for custom memory models:1. Specify Message Settings when you specify message categories (except Fatal).2. Use the message_level generic or parameter.3. Use a command stream or testbench command.By default, custom memory models display all the general message categories (Fatal,Error, Warning, Info, Timing, and X-handling). If you set a generic or parameter for amodel instance, that setting overrides the default behavior. In turn, if the commandstream or testbench interface is used, it overrides the generic or parameter value.Message Level ConstantsCustom memory models provide constants for setting message levels on eachinstantiated model. The constants described in Table 39 are defined in mempro_pkg.v(for Verilog simulators) and mempro_pkg.vhd (for VHDL simulators).You can combine these constants to get any combination of messages. The followingVerilog and VHDL code fragments define a model instantiation having timing,X-handling, and warning (as well as fatal) messages enabled.Verilogbank1.message_level = `SLM_XHANDLING | `SLM_TIMING | `SLM_WARNING,VHDLTable 39: Custom Memory Model Message ConstantsConstantValue a DescriptionSLM_ERROR 1 Fatal and error messages generated.SLM_WARNING 2 Fatal and warning messages generated.SLM_TIMING 4 Fatal and timing messages generated.SLM_XHANDLING 8 Fatal and X-handling messages generated.SLM_INFO 16 Fatal messages generated. Note: Using this bit can addlarge amounts of memory cycle information to thetranscript, considerably slowing simulation.SLM_ALL_MSGS 2 32 −1 All message types generated.SLM_NO_MSGS 0 Only fatal messages generated.a. Note that bits 5 through 31 are unused but reserved.message_level => (SLM_TIMING + SLM_XHANDLING + SLM_WARNING),284 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory ModelsInstantiating Custom Memory ModelsYou instantiate custom memory models just as you would any other HDL models, asshown in the following examples using DRAM.Verilog Instantiationdram1x64 bank1( .ras ( rasr ),.ucas ( ucasr ),.lcas ( lcasr ),.we ( wer ),.oe ( oer ),.a ( adrr ),.dq ( dataw ));defparam bank1.model_id = 10,bank1.memoryfile = "dram.dat",bank1.message_level = `SLM_XHANDLING | `SLM_TIMING | `SLM_WARNING,bank1.default_data = 64'hxxx;VHDL InstantiationU1 : dram1x64generic map ( model_id => 10,memoryfile => "dram.dat",message_level => (SLM_TIMING + SLM_XHANDLING + SLM_WARNING),default_data => "XXXX");port map( a => adrw,dq=> dataw,ras=> rasw,lcas=> lcasw,ucas=> ucasw,we=> wew,oe => oew );October 6, 2003 Synopsys, Inc. 285
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Simulator Configuration Guide for Synopsys Models

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