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Simulator Configuration Guide for Synopsys Models

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<strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Appendix B: Using Custom Memory <strong>Models</strong>VHDL Interface CodeThe VHDL interface code is contained in the following files:slm_hdlc.vhd <strong>Simulator</strong>-specific HDL-to-C interface code.mempro_pkg.vhd Module containing the VHDL implementation of thetestbench interface.These files are located in the $LMC_HOME/sim/simulator/src directory.Verilog Routines and Interface CodeThese files define the PLI routines and interface commands <strong>for</strong> Verilog simulators:slm_pli.oPLI routines. This file is located in the$LMC_HOME/lib/plat<strong>for</strong>m.lib directory.mempro_pkg.vControlling MessagesVerilog testbench task definitions <strong>for</strong> interface commands.This file is located in the $LMC_HOME/sim/pli/src directory.The messages used by custom memory models are grouped into categories that you canenable or disable individually <strong>for</strong> each model instance. Several message categoriesapply to all models, and you can define additional categories <strong>for</strong> specific models ormodel types. These are the general message categories:●●●●●●Fatal messages are always enabled. When a fatal error is detected, the simulationreports the message, then stops immediately. For example, referencing an unknownmemory model instance handle causes a fatal error.Error messages apply to incorrect situations from which the model can recover,allowing simulation to continue. For example, a custom memory model generatesan error message when it receives a command that would put it in an illegal state.Warning messages apply to situations that users may want to check, but are notnecessarily wrong. For example, custom memory models generate warningmessages when significant address bits are ignored.Info messages tell you of the status or behavior of the model. For example, when acustom memory model is initialized from a file, an info message is generated.Timing messages report timing constraint violations, such as occur with setup orpulse-width violations.X-handling messages report instances in which unknowns are sampled on inputports when valid data was expected.October 6, 2003 <strong>Synopsys</strong>, Inc. 283

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