Simulator Configuration Guide for Synopsys Models

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Appendix B: Using Custom Memory ModelsSimulator Configuration GuideConfiguring Custom Memory ModelsRegardless of which simulator you are using, you must configure your custom memorymodels by defining the required parameters or attributes shown in Table 38 for eachmodel instance in your design. You configure custom memory models when youinstantiate them in your design using these generics or parameters.Table 38: Custom Memory Model Generic/Parameter DescriptionsName Data Type Descriptionmodel_idmodel_aliasIntegerStringEither the model_id or model_alias generic or parameterspecifies a unique user handle for a specified model instance.This user handle is used to address a memory model usingtestbench commands.Note: You do not need to assign all custom memory modelinstances a model_id or model_alias, but only those instanceson which you will use the testbench interface. However, eachmodel with a model_id or model_alias must be assigned aunique handle.memoryfile String Specifies the file name of the memory image file to preloadduring model initialization. If memoryfile is set to a nullstring (memoryfile = “”), memory image preloading duringinitialization is disabled. Supported file formats areSmartModel Memory Image, Motorola S-Record, Intel Hex,and Verilog $readmemh. Memory models can also be loadedusing the mem_load command.default_data String Specifies the default data returned from all uninitializedmemory addresses.Note: Models in non-volatile memory classes may not havetheir Default Memory Value set to anything except all ones.Any other setting is ignored.message_level Integer Specifies the type or types of messages returned by themodel. For a detailed description of message types, refer to“Controlling Messages” on page 283.AttentionThe spelling, case (upper/lower), and argument types of generics andparameters used by custom memory models are not always the same asthose used by standard binary DWMM models. Be sure to follow theappropriate conventions for your model.282 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory ModelsVHDL Interface CodeThe VHDL interface code is contained in the following files:slm_hdlc.vhd Simulator-specific HDL-to-C interface code.mempro_pkg.vhd Module containing the VHDL implementation of thetestbench interface.These files are located in the $LMC_HOME/sim/simulator/src directory.Verilog Routines and Interface CodeThese files define the PLI routines and interface commands for Verilog simulators:slm_pli.oPLI routines. This file is located in the$LMC_HOME/lib/platform.lib directory.mempro_pkg.vControlling MessagesVerilog testbench task definitions for interface commands.This file is located in the $LMC_HOME/sim/pli/src directory.The messages used by custom memory models are grouped into categories that you canenable or disable individually for each model instance. Several message categoriesapply to all models, and you can define additional categories for specific models ormodel types. These are the general message categories:●●●●●●Fatal messages are always enabled. When a fatal error is detected, the simulationreports the message, then stops immediately. For example, referencing an unknownmemory model instance handle causes a fatal error.Error messages apply to incorrect situations from which the model can recover,allowing simulation to continue. For example, a custom memory model generatesan error message when it receives a command that would put it in an illegal state.Warning messages apply to situations that users may want to check, but are notnecessarily wrong. For example, custom memory models generate warningmessages when significant address bits are ignored.Info messages tell you of the status or behavior of the model. For example, when acustom memory model is initialized from a file, an info message is generated.Timing messages report timing constraint violations, such as occur with setup orpulse-width violations.X-handling messages report instances in which unknowns are sampled on inputports when valid data was expected.October 6, 2003 Synopsys, Inc. 283
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Simulator ConfigurationGuide for Sy
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Page 268 and 269: Appendix A: Using LMTV with Synopsy
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Simulator Configuration Guide for Synopsys Models

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