Simulator Configuration Guide for Synopsys Models

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Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_status() or $lai_status()Use these commands to report the current status of the model instance inst_path. Thereport includes the names and values of internal windows.Syntax$lm_status (inst_path)$lai_status (inst_path);Argumentsinst_pathThe path name to the SmartModel instance whosestatus is to be reported.ExamplesThe following example shows the output of the $lm_status() command for modelinstance “U1”.C1 > $lm_status(U1);Note: Model template: memVersion: not availableInstanceName: DESIGN.U1TimingVersion: MEM-0DelayRange: MAXMemoryFile: memory.1Timing Constraints: OnSmartModel Instance DESIGN.U1(mem:MEM-0), at time 1000.0 nsNote: SmartModel Windows Description:UMEM[2048] "2K x 8 Static RAM":SmartModel Windows not enabled for this model.SmartModel Instance DESIGN.U1(mem:MEM-0), at time 1000.0 ns280 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory ModelsBUsing Custom Memory ModelsThe DesignWare Memory Model technology software package supports custommemory models. These custom models are produced in Verilog or VHDL, and do notuse the SWIFT interface, but do require simulator-specific PLI/CLI/FLI code that mustbe bound into the supported simulator executable. Table 37 lists the simulators thatsupport custom memory models:Table 37: Simulators That Support Custom Memory ModelsVerilog SimulatorsVCSNC-VerilogMTI VerilogVHDL SimulatorsSciroccoMTI VHDLNC-VHDLSee the following sections for information on using custom memory models:● “Configuring Custom Memory Models” on page 282● “Controlling Messages” on page 283● “Instantiating Custom Memory Models” on page 285● “Using Custom Memory Models with VCS” on page 286● “Using Custom Memory Models with NC-Verilog” on page 289● “Using Custom Memory Models with MTI Verilog” on page 290● “Using Custom Memory Models with Scirocco” on page 292● “Using Custom Memory Models with MTI VHDL” on page 294● “Using Custom Memory Models with NC-VHDL” on page 296● “Using Custom Memory Models with VERA” on page 299October 6, 2003 Synopsys, Inc. 281
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Simulator ConfigurationGuide for Sy
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Simulator Configuration Guide for Synopsys Models

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