Simulator Configuration Guide for Synopsys Models

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideInstantiating FlexModels with C-only Command ModeC-only Command Mode is how you use FlexModels on SWIFT simulators withstandard FlexModel integrations. With C-only Command Mode, all model commandscome from an external compiled C program that you point to using the FlexCFileSWIFT parameter. For users familiar with Synopsys Hardware Verification models, thisis similar to setting the PCLFile parameter to point to the location of a compiled PCLprogram. In addition, you must also set the FlexModelId parameter, which does not havea default value. To generate model wrappers and instantiate models, you use the samesimulator-specific procedures as you would for traditional SmartModels. Note thatFlexModels are shipped with generated wrapper files for Verilog and VHDLtestbenches. These wrapper files are one of the file sets copied into your workingdirectory using the flexm_setup utiltiy.The individual FlexModel datasheets document the command syntax and examples forissuing model commands from Verilog, VHDL, VERA, or C. However, only simulatorswith custom integrations allow you to issue FlexModel commands from Verilog,VHDL, VERA, C, or some combination of these. SWIFT simulators with standardintegrations must stick to C-only Command Mode for issuing commands toFlexModels.To use C-only Command Mode, follow these steps:1. If you are using an HDL-based simulator, generate a model wrapper file(model_fx.v or model_fx.vhd) using your simulator vendor’s procedure. Use themodel wrapper to instantiate the model in your design. Add the FlexCFile parameter(for _fx models) or FlexModelSrc_cmd_stream parameter (for _fz models) to themodel instantiation and point it to the location of your_compiled_C_file that youcreate to drive commands into the model. Modify other SWIFT parameters in themodel wrapper as needed. Here are some examples for how to instantiate an _fxmodel for use with C-only Command Mode:VHDL:U1: pcimasterGENERIC MAP(FlexModelId => "modelId_1",FlexCFile => "./tb.o",FlexTimingMode => "1",TimingVersion => "pcimaster",DelayRange => "MAX"Verilog:defparamu1.FlexModelId = "modelId_1",u1.FlexCFile = "./tb.o",u1.FlexTimingMode = "1",26 Synopsys, Inc. October 6, 2003