Simulator Configuration Guide for Synopsys Models

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Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideSimulator: Scirocco1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. Create slm_lib and work directories, as shown in the following examples:% mkdir ./slm_lib% mkdir ./work3. Create the logical to physical mapping for the slm_lib, work, and default libraries bymodifying your local synopsys_sim.setup file to include the following lines:WORK > DEFAULTDEFAULT : ./workSLM_LIB : ./slm_lib4. Set your simulation timebase by modifying your local synopsys_sim.setup file toinclude a TIMEBASE entry, as shown in the following example:TIMEBASE = PS5. Compile the required Synopsys libraries into the slm_lib library, as shown in thefollowing example:% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/mempro_pkg.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.6. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.components.all;USE SLM_LIB.mempro_pkg.all;7. Create the model’s bused wrapper as shown in the following example:% $SYNOPSYS_SIM/platform/sim/bin/create_smartmodel_lib -create \-srcdir . -model model_mxThis step produces a components.vhd file and an entities.vhd file. The model_mxmodel is defined in the entities.vhd file.8. Instantiate the model_mx model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.258 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsHintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).9. Analyze the entities.vhd and components.vhd files, as shown in the followingexample:% vhdlan -w slm_lib components.vhd% vhdlan -w slm_lib entities.vhdNoteThese examples work for event-based simulation. For information on cyclebasedoperation, see the Scirocco Reference Manual.10. Analyze your testbench as shown in the following example:% vhdlan testbench.vhd11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim -vhpi slm_vhpi:foreignINITelab:cpipeb. If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe designOctober 6, 2003 Synopsys, Inc. 259
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Simulator ConfigurationGuide for Sy
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 8: Using Scirocco with Syno
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Page 268 and 269: Appendix A: Using LMTV with Synopsy
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Simulator Configuration Guide for Synopsys Models

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