12.07.2015 Views

Simulator Configuration Guide for Synopsys Models

Simulator Configuration Guide for Synopsys Models

Simulator Configuration Guide for Synopsys Models

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

Chapter 9: Using VERA with <strong>Synopsys</strong> <strong>Models</strong><strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Linux:% gcc -c -fPIC -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% gcc -shared -o ./libpli.so \./veriuser.o $LMC_HOME/lib/x86_linux.lib/lmtv.o \$LMC_HOME/lib/x86_linux.lib/slm_pli_dyn.so $VERA_HOME/lib/libSysSciTaskPIC.aSolaris:% /usr/ucb/cc -c -KPIC -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% /usr/ucb/cc -G -z text -o ./libpli.so \./veriuser.o $LMC_HOME/lib/sun4Solaris.lib/lmtv.o \$LMC_HOME/lib/sun4Solaris.lib/slm_pli_dyn.so $VERA_HOME/lib/libSysSciTaskPIC.a5. Modify your environmental library path to include the directory path to your locallibpli library, as follows:HP-UX:% setenv SHLIB_PATH dir_path_to_libpli.sl:$SHLIB_PATHLinux and Solaris:% setenv LD_LIBRARY_PATH dir_path_to_libpli.so:$LD_LIBRARY_PATH6. Set your SSI_LIB_FILES environmental variable to include the path to yourlocal VERA UDF library, as follows:% setenv SSI_LIB_FILES path_to_vera_local.dl7. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For in<strong>for</strong>mation on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.8. Generate a bit-blasted Verilog wrapper file <strong>for</strong> the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.9. Generate a bused Verilog wrapper file <strong>for</strong> the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxThis step produces a bused Verilog wrapper file named model_mx_bw.v.256 <strong>Synopsys</strong>, Inc. October 6, 2003

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!