Simulator Configuration Guide for Synopsys Models

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Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideHere’s an example of a combined VERA/DWMM-compatible veriuser.c file:/* README:To run Verilog 2.2 only with Vera, use this veriuser.c as is.For other versions of Verilog you may need to edit this template.If you need to link in additional tasks, you will need to combinethis veriuser.c with your own (if you have not done this before,please see the directions in Cadence's documentation).*/#ifdef WIN32# define Dll_Export __declspec(dllexport)#else# define Dll_Export#endif#include "veriuser.h"#include "acc_user.h"#ifndef accVersionLatest#include "vxl_acc_user.h"#include "vxl_veriuser.h"#endif#include "vmc_veri_funext.h"#include "ccl_lmtv_include.h"extern int pli_slm_post();extern int slm_mempro_handle();extern int slm_mempro_width_info();Dll_Export char *veriuser_version_str ="=== Verilog with Synopsys Vera ===\n";Dll_Export bool err_intercept(level,facility,code)int level;char *facility;char *code;{return(true);}Dll_Export s_tfcell veriusertfs[] ={/*** Template for an entry:* { usertask|userfunction, data,* checktf(), sizetf(), calltf(), misctff(),* "$tfname", forwref?, Vtool?, ErrMsg?* },254 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models* Example:* { usertask, 0, my_check, 0, my_func, my_misctf, "$my_task"* },* ***/{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post", true },{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post_hdl", true },{ usertask, 0, 0, 0, slm_mempro_handle, 0, "$slm_mempro_handle", true },{ usertask, 0, 0, 0, slm_mempro_width_info, 0, \"$slm_mempro_width_info", true },# include "vmc_veri_fundef.c"#include "ccl_lmtv_include_code.h"/*** add user entries here ***/{0} /*** final entry must be 0 ***/};Dll_Export void init_usertfs(){p_tfcell usertf;for (usertf = veriusertfs; usertf; usertf++){if (usertf->type == 0)return;mti_RegisterUserTF(usertf);}}#endifDll_Export int (*endofcompile_routines[])() ={/*** my_eoc_routine, ***/0 /*** final entry must be 0 ***/};4. Build a local libpli library as follows:HP-UX:% /bin/c89 -c +Z -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% /usr/ccs/bin/ld -b -o ./libpli.sl \./veriuser.o $LMC_HOME/lib/hp700.lib/lmtv.o \$LMC_HOME/lib/hp700.lib/slm_pli_dyn.sl $VERA_HOME/lib/libSysSciTaskPIC.aOctober 6, 2003 Synopsys, Inc. 255
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Page 208 and 209: Chapter 9: Using VERA with Synopsys
Page 262 and 263: Chapter 10: Using SystemC with Syno
Page 268 and 269: Appendix A: Using LMTV with Synopsy
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Simulator Configuration Guide for Synopsys Models

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