Simulator Configuration Guide for Synopsys Models

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Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide9. Instantiate the model in your design using the bused wrapper (model_mx_bw) or thebit-blasted wrapper (model_mx). Define the ports, testbench pins, and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters, though you can override these values in your testbench ifneeded.For details on the required SWIFT parameters and DWMM instantiation examples,see “DesignWare Memory Model SWIFT Parameters” on page 29.Here is an example of a typical bused wrapper file:PORT MAP (a => sm_a,cs_n => sm_cs_n,be_n => sm_be_n,io => sm_io,oe_n => sm_oe_n,we_n => sm_we_n);SIGNAL sm_a : STD_LOGIC_VECTOR(17 DOWNTO 0);SIGNAL sm_cs_n : STD_LOGIC;SIGNAL sm_be_n : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_io : STD_LOGIC_VECTOR(16 DOWNTO 1);SIGNAL sm_oe_n : STD_LOGIC;SIGNAL sm_we_n : STD_LOGIC;SIGNAL sm_dout_valid : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_wr_data : STD_LOGIC_VECTOR(0 TO 15);HintFor model-specific instantiation examples, see the model datasheets. Youcan cut and paste the instantiation directly from the model datasheet and intoyour testbench. Be sure to map signal names in your design to the model’sports. You can access the model datasheet for your version of the model withthe sl_browser tool ($LMC_HOME/bin/sl_browser).252 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsAttentionFor best performance, use version 4.0 or later of NC-VHDL. NC-VHDLversion 4 and higher allow you to load multiple dynamic libraries containingC code. To use this means of loading the DWMM routines, include thefollowing option in the line invoking ncsim:ncsim -loadfmi libfmi_ml.so:slm_boot libfmi_ml.so (or .sl on HP-UX platforms) contains the library table andbootstrap function needed by the dynamic loader included in NC-VHDLversion 4.0 and above. This method eliminates the need to link libfmi_ar.awith your other external C (foreign language) modules to produce a singlelibfmi.so that incorporates all foreign language modules in a single library.For more information about using the NC-VHDL with multiple dynamiclibraries, see your Cadence simulator documentation.Simulator: NC-Verilog1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. Copy the VERA specific veriuser.c file:% cp $VERA_HOME/lib/veriuser.c .3. Edit the local copy of the veriuser.c file to add the lines required for DWMM.a. Add the required DWMM include header and extern function declarations justbelow the VERA include header vmc_veri_funext.h:#include "ccl_lmtv_include.h"extern int pli_slm_post();extern int slm_mempro_handle();extern int slm_mempro_width_info();b. Add the DWMM s_tfcell entries to the global veriusertfs table:{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post", true },{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post_hdl", true },{ usertask, 0, 0, 0, slm_mempro_handle, 0, "$slm_mempro_handle", true },{ usertask, 0, 0, 0, slm_mempro_width_info, 0, "$slm_mempro_width_info", true },c. Add the required DWMM include code just below the VERA include codeentry vmc_veri_fundef.c:#include "ccl_lmtv_include_code.h"October 6, 2003 Synopsys, Inc. 253
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Simulator ConfigurationGuide for Sy
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 8: Using Scirocco with Syno
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Simulator Configuration Guide for Synopsys Models

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