Simulator Configuration Guide for Synopsys Models

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide9. Instantiate the model in your design using the bused wrapper (model_mx_bw) or thebit-blasted wrapper (model_mx). Define the ports, testbench pins, and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters, though you can override these values in your testbench ifneeded.For details on the required SWIFT parameters and DWMM instantiation examples,see “DesignWare Memory Model SWIFT Parameters” on page 29.Here is an example of a typical bused wrapper file:PORT MAP (a => sm_a,cs_n => sm_cs_n,be_n => sm_be_n,io => sm_io,oe_n => sm_oe_n,we_n => sm_we_n);SIGNAL sm_a : STD_LOGIC_VECTOR(17 DOWNTO 0);SIGNAL sm_cs_n : STD_LOGIC;SIGNAL sm_be_n : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_io : STD_LOGIC_VECTOR(16 DOWNTO 1);SIGNAL sm_oe_n : STD_LOGIC;SIGNAL sm_we_n : STD_LOGIC;SIGNAL sm_dout_valid : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_wr_data : STD_LOGIC_VECTOR(0 TO 15);HintFor model-specific instantiation examples, see the model datasheets. Youcan cut and paste the instantiation directly from the model datasheet and intoyour testbench. Be sure to map signal names in your design to the model’sports. You can access the model datasheet for your version of the model withthe sl_browser tool ($LMC_HOME/bin/sl_browser).252 Synopsys, Inc. October 6, 2003