Simulator Configuration Guide for Synopsys Models

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Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide12. Invoke the simulator as shown in the following examples:HP-UX:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl designSolaris:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so designLinux:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so designSimulator: NC-VHDL1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. Edit your cds.lib file to specify the logical library slm_lib for DWMM models:DEFINE slm_lib ./slm_libNoteAlso, make sure your cds.lib and hdl.var files contain the correctSOFTINCLUDE statements for running NC-VHDL.3. Create a directory named slm_lib:mkdir slm_lib4. Compile the required Synopsys libraries into the slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhdNoteIgnore the warning: ncvhdl_p: *W,FATSPB (slm_hdlc.vhd,72).% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd250 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsAttentionYou can omit steps 5 and 6, below, if you already performed those tasks asdescribed in “Using SmartModels with NC-VHDL” on page 109.5. Run the ncshell utility to generate a wrapper for the model you want to use:% ncshell -import swift -into vhdl model_mx -nocompile -work slm_libThis step produces in the slm_lib work directory a bit-blasted wrapper file(model_mx.vhd) and a component declaration file (model_mx_comp.vhd) for thespecified model.6. Compile the bit-blasted wrapper and component file:% ncvhdl -w slm_lib model_mx.vhd% ncvhdl -w slm_lib model_mx_comp.vhd7. If you want to use a bused wrapper for the model, do the following:a. Use the following command to produce a bused wrapper file namedmodel_mx_bw.vhd:% $LMC_HOME/bin/vsg -bit2bus vhdl model_mxb. Edit the model_mx_bw.vhd file to add Library and Use statements to the top ofthe file:LIBRARY SLM_LIB;USE SLM_LIB.smartmodels.all;c. Compile the bused wrapper:% ncvhdl -w slm_lib model_mx_bw.vhdAttentionIf you want to use the bused model wrapper, you must add appropriatecomponent declarations to your testbench or edit a component file alreadyincluded in your testbench for multiple SWIFT models, specifying ports andgenerics as required.8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.smartmodels.all;use slm_lib.mempro_pkg.all;October 6, 2003 Synopsys, Inc. 251
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 8: Using Scirocco with Syno
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Simulator Configuration Guide for Synopsys Models

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