Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using SmartModels with ModelSim Verilog” onpage 61).7. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.8. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.9. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxThis step produces a bused Verilog wrapper file named model_mx_bw.v.10. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).11. Compile your design as shown in the following example:% vlog testbench.v model_mx.v model_mx_bw.v \vera_testbench_shell.v \+incdir+$LMC_HOME/sim/pli/srcOctober 6, 2003 Synopsys, Inc. 249