Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models11. Edit the model_mx_bw.vhd file to add Library and Use statements, as shown in thefollowing example:LIBRARY SLM_LIB;USE SLM_LIB.comp.all;12. Compile the model’s bused wrapper, as shown in the following example:% vcom -93 model_mx_bw.vhdAttentionTo use the bused model wrapper, you must add appropriate componentdeclarations to your testbench or edit a component file already included inyour testbench for multiple SWIFT models, specifying ports and generics asrequired.13. Instantiate the model in your design using either the bit-blasted wrapper(model_mx) or the bused wrapper (model_mx_bw). Define the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.14. Compile the VERA shell file created during the VERA compilation of your VERAtestbench, as follows:% vcom -93 _shell.vhdHintFor model-specific instantiation examples, see the individual modeldatasheets. You can copy the model instantiation directly from the modeldatasheet and paste it into your testbench. Be sure to map signal names in yourdesign to the model’s ports. You can access the model datasheet for yourmodel version using the sl_browser tool ($LMC_HOME/bin/sl_browser).15. Compile your testbench:% vcom -93 testbench.vhd16. Invoke MTI VHDL and simulate your design:% vsim testbench_configurationSimulator: MTI Verilog1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Build a local veriuser library as follows:October 6, 2003 Synopsys, Inc. 247