Simulator Configuration Guide for Synopsys Models

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideVERA Testbench Paired with Top-level VHDL Testbench1. Top-level VHDL Testbench Exampleentity top if end top;architecture test of top is...U1 : am29f002bb_mx--For DesignWare Memory Models, set ID of U1generic map (ModelId => “5”)port map (a => adq => dqwe_n => we_noe_n => oe_nreset_n => reset_n);2. VERA Testbench Exampleprogram model_test {MemPro inst1;}inst1 = new(5); // inst1 corresponds to U1 in VHDL codeif (inst1.showStatus()!= SLM_TESTBENCH_SUCCESS){}//Error handling234 Synopsys, Inc. October 6, 2003