Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models// Peek at some memory locationsmem1.peek( 128'hFF, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);mem1.peek( 128'h00, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);// Unload part of the memorymem1.unload( 128'ha0, 128'hff, status);// Dump the memory contents in Verilog formatmem1.dump( "./memory_images/sram2.mif", `SLM_FMT_VLOG, 128'h00,128'hffff, status);printf(" Dump status = %d\n", status);} // end of program DWMM_testA top-level HDL testbench file is required to connect your VERA testbench to theDWMM model. The following two VERA testbench examples show a VERA testbenchpaired with a Verilog testbench top module and a VERA testbench paired with a VHDLtestbench top module.VERA Testbench Paired with Top-level Verilog Testbench1. Top-level Verilog Testbench Examplemodule top;...am29f002bb_mx U1 (.a(a) , .dq(dq) , .we_n(we_n) , .ce_n(ce_n) ,.oe_n(oe_n), .reset_n(reset_n));// For DesignWare Memory Models, set ID of U1defparamU1.ModelId = “5”;2. VERA Testbench Exampleprogram model_test {MemPro inst1;}inst1 = new(5); // inst1 corresponds to U1 in Verilog testbenchif (inst1.showStatus()!= SLM_TESTBENCH_SUCCESS) {//Error handling}October 6, 2003 Synopsys, Inc. 233