Simulator Configuration Guide for Synopsys Models

More documents

Recommendations

Info

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideMemPro mem1;//// Start of DWMM_test ////// Create an instance of the model with model_id = 5mem1 = new(5);if (mem1.showStatus()!= SLM_TESTBENCH_SUCCESS){printf (“Error: failure instantiating Model/n”);exit (1);}// Retrieve the instance infomem1.instance_info( data_width, addr_width, instance_name,class_name, status);printf( "instance_info status = %d\n", status);if (status == SIM TESTBENCH_SUCCESS) {printf( "Data_width = %d\n", data_width);printf( "Addr_width = %d\n", addr_width);printf( "Instance_name = %s\n", instance_name);printf( "Class_name = %s\n", class_name);}else {printf ("Error: Could not set info for mem1\n");exit();}// Set the message levelmem1.set_message_level( SLM_ALL_MSGS, status); }printf(" Set msg level status = %d\n", status);// Retrieve the message levelmem1.get_message_level( msgLevel, status);printf(" Get msg level status = %d\n", status);printf(" msg level = %d\n", msgLevel);if ( msgLevel != SLM_ALL_MSGS) {printf("Error: incorrect message level returned - %d\n",msgLevel);}// Poke some values into memorymem1.poke( 128'h00, 66'h1f, status);mem1.poke( 128'hFF, 66'hff, status);// Load a memory image filemem1.load( "./memory_images/sram1.mif", status);232 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models// Peek at some memory locationsmem1.peek( 128'hFF, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);mem1.peek( 128'h00, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);// Unload part of the memorymem1.unload( 128'ha0, 128'hff, status);// Dump the memory contents in Verilog formatmem1.dump( "./memory_images/sram2.mif", `SLM_FMT_VLOG, 128'h00,128'hffff, status);printf(" Dump status = %d\n", status);} // end of program DWMM_testA top-level HDL testbench file is required to connect your VERA testbench to theDWMM model. The following two VERA testbench examples show a VERA testbenchpaired with a Verilog testbench top module and a VERA testbench paired with a VHDLtestbench top module.VERA Testbench Paired with Top-level Verilog Testbench1. Top-level Verilog Testbench Examplemodule top;...am29f002bb_mx U1 (.a(a) , .dq(dq) , .we_n(we_n) , .ce_n(ce_n) ,.oe_n(oe_n), .reset_n(reset_n));// For DesignWare Memory Models, set ID of U1defparamU1.ModelId = “5”;2. VERA Testbench Exampleprogram model_test {MemPro inst1;}inst1 = new(5); // inst1 corresponds to U1 in Verilog testbenchif (inst1.showStatus()!= SLM_TESTBENCH_SUCCESS) {//Error handling}October 6, 2003 Synopsys, Inc. 233
Page 1:
Simulator ConfigurationGuide for Sy
Page 4 and 5:
ContentsSimulator Configuration Gui
Page 6 and 7:
ContentsSimulator Configuration Gui
Page 8 and 9:
FiguresSimulator Configuration Guid
Page 10 and 11:
TablesSimulator Configuration Guide
Page 12 and 13:
PrefaceSimulator Configuration Guid
Page 14 and 15:
Page 16 and 17:
Page 18 and 19:
Chapter 1: Using Synopsys Models wi
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Chapter 2: Using VCS with Synopsys
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Chapter 3: Using ModelSim Verilog w
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
Chapter 4: Using ModelSim VHDL with
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Chapter 5: Using NC-Verilog with Sy
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Chapter 6: Using NC-VHDL with Synop
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Chapter 7: Using QuickSim II with S
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
.Chapter 7: Using QuickSim II with
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183: Chapter 7: Using QuickSim II with S
Page 192 and 193: Chapter 8: Using Scirocco with Syno
Page 208 and 209: Chapter 9: Using VERA with Synopsys
Page 262 and 263: Chapter 10: Using SystemC with Syno
Page 268 and 269: Appendix A: Using LMTV with Synopsy
Page 282 and 283:
Appendix B: Using Custom Memory Mod
Page 284 and 285:
Page 286 and 287:
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Page 296 and 297:
Page 298 and 299:
Page 300 and 301:
Page 302 and 303:
IndexSimulator Configuration Guide$
Page 304 and 305:
IndexSimulator Configuration Guidef
Page 306 and 307:
IndexSimulator Configuration GuideL
Page 308 and 309:
IndexSimulator Configuration GuideQ
Page 310 and 311:
IndexSimulator Configuration GuideS
show all

Simulator Configuration Guide for Synopsys Models

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?