Simulator Configuration Guide for Synopsys Models

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuidePrerequisites to Using the VERA with the DesignWareMemory Model InterfaceThe discussion of the VERA design flow assumes that you have already generated orobtained your memory models, have instantiated the models in your design, and havecreated both the top-level HDL testbench and the VERA testbench.Design Flow for DesignWare Memory Models with VERAFigure 10 on page 229 shows the design flow. First, add DWMM model commands tothe VERA testbench, vera_testbench.vr. Next, to be able to use the models with theVERA User-Defined Functions (UDF) interface, you must build a simulator-specificVERA dynamic library, to be linked into your simulator executable. Next, you compilethe VERA testbench, along with the Synopsys-supplied source files lstmodel.vr andmempromodel.vr, to obtain object files *.vro. In addition, the compile process generatesthe vera_shell.{v, vhd} file.Next, you build the simulator executable, linking in the HDL files (model.{v, vhd}, thetop-level HDL testbench, and vera_shell.{v, vhd}). Finally, you run the simulation.228 Synopsys, Inc. October 6, 2003