Simulator Configuration Guide for Synopsys Models

More documents

Recommendations

Info

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originmodel.{v, vhd}lstmodel.vrhmempromodel.vrhlstmodel.vrmempromodel.vrThe DWMM file for the modelyou want to instantiate.Note: You instantiate aDesignware Memory Model inyour HDL testbench using apositive integer in a quoted stringfor the ModelId parameter.Example: “67”But, you then use a true integer toinstantiate the same model in yourVERA testbench.Example: ( 67 )For more information on how toinstantiate standard DWMMmodels, see “Using DesignWareMemory Models with SWIFTSimulators” on page 29.For more information on how toinstantiate custom DWMMmodels, see “Instantiating CustomMemory Models” on page 285.A file containing the externalclass declaration for the LstModelclass. This file is included in themempromodel.vrh file.The mempromodel header file.Contains definitions for theMemPro model class and formodel-specific constants useful inDWMM memory commands. Youinclude this header in your VERAtestbench.A VERA source file containingthe LstModel class definition.You compile this file for useduring the simulation.A VERA source file containingtestbench commands, along withthe MemPro model classdefinition for model instantiation.You compile this file for useduring simulation.Generate wrappers forinstantiating the models asexplained in the simulatorspecificchapters in thismanual.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.226 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originvera_testbench.vrThe user’s VERA testbench file,which creates MemPro classinstances and calls the DWMMtestbench methods.You compilethis file for use during simulation.You create this file with a texteditor.lstmodel.vromempromodel.vrovera_testbench.vrovera_shell.{v, vhd}design_testbench.top.{v,vhd}The object file after compilinglstmodel.vr. This file is usedduring simulation.The object file after compilingmempromodel.vr. This file is usedduring simulation.The object file after compilingvera_testbench.vr. This file isused during simulation.This file is the mediator betweenthe model and VERA, and is usedduring Verilog or VHDLcompilation.The top-level HDL testbench.This file is used during Verilog orVHDL compilation.You create this file when youcompile lstmodel.vr.You create this file when youcompile mempromodel.vr.You create this file when youcompile the VERA testbenchfile.This file is generated by VERAwhen you compile yourtestbench file.Create this file with a texteditor.design.{v, vhd} Your design. You created these files in orderto build your design.files_to_loadThis file contains the pathnamesof the VERA object fileslstmodel.vro, mempromodel.vro,and design_testbench.vro.Thesimulator looks in this file forVERA objects to load duringruntime.You create this file in a texteditor. The name is arbitrary.a. A vera_user.c file also exists in $VERA_HOME, but does not declare the MemPro andLstModel UDF functions, and does not work with DWMM. If you use a vera_user.c file otherthan the one provided in $LMC_HOME, make sure you include the function declarationsfound in the $LMC_HOME version.October 6, 2003 Synopsys, Inc. 227
Page 1:
Simulator ConfigurationGuide for Sy
Page 4 and 5:
ContentsSimulator Configuration Gui
Page 6 and 7:
ContentsSimulator Configuration Gui
Page 8 and 9:
FiguresSimulator Configuration Guid
Page 10 and 11:
TablesSimulator Configuration Guide
Page 12 and 13:
PrefaceSimulator Configuration Guid
Page 14 and 15:
Page 16 and 17:
Page 18 and 19:
Chapter 1: Using Synopsys Models wi
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Chapter 2: Using VCS with Synopsys
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Chapter 3: Using ModelSim Verilog w
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
Chapter 4: Using ModelSim VHDL with
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Chapter 5: Using NC-Verilog with Sy
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Chapter 6: Using NC-VHDL with Synop
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Chapter 7: Using QuickSim II with S
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
.Chapter 7: Using QuickSim II with
Page 176 and 177: Chapter 7: Using QuickSim II with S
Page 192 and 193: Chapter 8: Using Scirocco with Syno
Page 208 and 209: Chapter 9: Using VERA with Synopsys
Page 262 and 263: Chapter 10: Using SystemC with Syno
Page 268 and 269: Appendix A: Using LMTV with Synopsy
Page 276 and 277:
Appendix A: Using LMTV with Synopsy
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Appendix B: Using Custom Memory Mod
Page 284 and 285:
Page 286 and 287:
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Page 296 and 297:
Page 298 and 299:
Page 300 and 301:
Page 302 and 303:
IndexSimulator Configuration Guide$
Page 304 and 305:
IndexSimulator Configuration Guidef
Page 306 and 307:
IndexSimulator Configuration GuideL
Page 308 and 309:
IndexSimulator Configuration GuideQ
Page 310 and 311:
IndexSimulator Configuration GuideS
show all

Simulator Configuration Guide for Synopsys Models

Create successful ePaper yourself

Delete template?

Save as template?