Simulator Configuration Guide for Synopsys Models

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Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originmodel.{v, vhd}lstmodel.vrhmempromodel.vrhlstmodel.vrmempromodel.vrThe DWMM file for the modelyou want to instantiate.Note: You instantiate aDesignware Memory Model inyour HDL testbench using apositive integer in a quoted stringfor the ModelId parameter.Example: “67”But, you then use a true integer toinstantiate the same model in yourVERA testbench.Example: ( 67 )For more information on how toinstantiate standard DWMMmodels, see “Using DesignWareMemory Models with SWIFTSimulators” on page 29.For more information on how toinstantiate custom DWMMmodels, see “Instantiating CustomMemory Models” on page 285.A file containing the externalclass declaration for the LstModelclass. This file is included in themempromodel.vrh file.The mempromodel header file.Contains definitions for theMemPro model class and formodel-specific constants useful inDWMM memory commands. Youinclude this header in your VERAtestbench.A VERA source file containingthe LstModel class definition.You compile this file for useduring the simulation.A VERA source file containingtestbench commands, along withthe MemPro model classdefinition for model instantiation.You compile this file for useduring simulation.Generate wrappers forinstantiating the models asexplained in the simulatorspecificchapters in thismanual.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.226 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originvera_testbench.vrThe user’s VERA testbench file,which creates MemPro classinstances and calls the DWMMtestbench methods.You compilethis file for use during simulation.You create this file with a texteditor.lstmodel.vromempromodel.vrovera_testbench.vrovera_shell.{v, vhd}design_testbench.top.{v,vhd}The object file after compilinglstmodel.vr. This file is usedduring simulation.The object file after compilingmempromodel.vr. This file is usedduring simulation.The object file after compilingvera_testbench.vr. This file isused during simulation.This file is the mediator betweenthe model and VERA, and is usedduring Verilog or VHDLcompilation.The top-level HDL testbench.This file is used during Verilog orVHDL compilation.You create this file when youcompile lstmodel.vr.You create this file when youcompile mempromodel.vr.You create this file when youcompile the VERA testbenchfile.This file is generated by VERAwhen you compile yourtestbench file.Create this file with a texteditor.design.{v, vhd} Your design. You created these files in orderto build your design.files_to_loadThis file contains the pathnamesof the VERA object fileslstmodel.vro, mempromodel.vro,and design_testbench.vro.Thesimulator looks in this file forVERA objects to load duringruntime.You create this file in a texteditor. The name is arbitrary.a. A vera_user.c file also exists in $VERA_HOME, but does not declare the MemPro andLstModel UDF functions, and does not work with DWMM. If you use a vera_user.c file otherthan the one provided in $LMC_HOME, make sure you include the function declarationsfound in the $LMC_HOME version.October 6, 2003 Synopsys, Inc. 227
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Simulator Configuration Guide for Synopsys Models

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