Simulator Configuration Guide for Synopsys Models

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideDesignWare Memory Models with VERADesignWare Memory Models have an object-oriented VERA command interface youcan use to control the models from VERA, thereby retaining the benefits of the VERAverification language while using the DWMM testbench commands. For informationabout the DWMM VERA testbench commands, see the DesignWare Memory ModelUser’s Manual.DesignWare Memory Model VERA ClassesVERA implements a number of useful features of an object-oriented language. Thecustom DWMM-VERA interface provides a class that contains public method functionsso that a VERA testbench can access custom DWMM models. This class inherits thebase class LstModel features.Figure 9 shows the model hierarchy.LstModelCustomDWMMModelFigure 9: VERA Model Class HierarchyLstModel is an abstract or virtual class and cannot be instantiated directly in VERAtestbenches. Only an instance of a MemPro class can be created in a VERA testbench.The commands used to control DWMM models are public methods of the MemProclass. You can send DWMM models commands from VERA only through an instanceof the MemPro class.The following section refers often to user-defined functions (UDF). UDFs are “bodies”(written in C) of VERA methods. They are much like Verilog, PLI, or VHDL functions.UDFs must be declared in a VERA header (.vrh) file to be usable by VERA programs.They must also be compiled and linked into the simulator executable.224 Synopsys, Inc. October 6, 2003