Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsWith VERA 5.0 and VCS 6.01, two new VCS compile switches, (-vera and-vera_dbind, were added. These switches automatically link into the VERA libraryand include platform-specific VCS compiler switches. You need to use the+vera_udf=vera_local.dl switch when compiling with –vera or –vera_dbind. Fordetails please refer to VERA 5.0 Release Notes.The -vera switch can only be used for designs that do not use dynamic binding. Thismeans that the system clock has to be used in the FlexModel VERA interface. Touse the system clock, the model constructor must leave out the clk_path argumentand default to the system clock(new(InstName, “”))If a direct connection to the HDL clock is desired you must use the –vera_dbindswitch and specify the full path to the clock. The VERA interface then uses thesignal_connect function to perform dynamic binding.The model’s VERA interface will issue a warning, informing you that you havespecified a clock instead of using the default system clock. This warning can beswitched off by compiling the flexmodel_pkg.vr file with the -DNO_WARNINGpreprocessor flag.3. Create a file for VERA to load at runtime.This step assumes that the vro files are in the current working directory. You need tocreate a file that looks like the following example. The file name for this examplefile is files_to_load:./lstmodel.vro./swiftmodel.vro./flexmodel_pkg.vro./model_pkg.vro./testbench.vroFor more information, refer to the documentation on vera_mload in the VERA UserGuide.4. Run the simv executableAdd the +vera_udf and +vera_mload switches, as shown in the following example:% simv +vera_udf=./vera_local.dl +vera_mload = files_to_load \+vera_finish_on_endNoteThe +vera_finish_on_end switch prevents your simulation from endingprematurely in cases where the VERA testbench completes before theVerilog testbench.October 6, 2003 Synopsys, Inc. 217