Simulator Configuration Guide for Synopsys Models

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideNoteIf you are building the VERA dynamic library on Solaris, do not use the -Bsymbolic switch. Using this switch results in unresolved symbol warnings.5. Create a VERA testbench.For details, refer to “Creating a VERA Testbench” on page 210.6. Compile the VERA testbench.Although you need to include only the flexmodel_pkg.vrh and model_pkg.vrh filesin your VERA testbench, the VERA compiler needs to find the other header filestoo; therefore, you need to include the path to the VERA header files included inLMC_HOME. The following is a sample compile script:% vera -cmp -I$LMC_HOME/sim/vera/src -I/workdir/src/vera \vera_testbench.vrThis step produces two files: testbench.vro and testbench.vshell.7. Run the VERA testbench in a Verilog or VHDL simulation environment.When you run the Verilog or VHDL simulator, the VERA simulator needs to loadyour compiled VERA object files. You also need to load the following VERA objectfiles:• lstmodel.vro• swiftmodel.vro• flexmodel_pkg.vro• model_pkg.vro• testbench.vroFor more information on loading VERA object files, refer to the VERA User Guide.AttentionTo prevent your simulation from ending prematurely in cases where theVERA testbench completes before the Verilog/VHDL testbench, use the+vera_finish_on_end switch on your simulator invocation line.214 Synopsys, Inc. October 6, 2003