Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsVERA Testbench ExampleThe following example shows how to incorporate FlexModels in a VERA testbench.#include #include “flexmodel_pkg.vrh”here#include “model_pkg.vrh”constants defined hereprogram model_test{// Vera Defines// FlexModel generic constants defined// Model class, and model-specific/** Create an instance of the model, argument 1 to the* constructor is the string name of the instance in* top level Verilog/VHDL testbench.* argument 2 is the path to the models clock pin* Here the assumption made is that the model is* instantiated in a Verilog testbench* Since the constructor has been called, this will* return at the next posedge of u1.CLK.*/ModelFx model_1 = new(“modelInstName_1”, “u1.CLK”);// Create another instance, since time has already elapsed// above, this call will return immediately.ModelFx model_2 = new(“modelInstName_2”, “u2.CLK”);// NOTE : This example assumes that the aguments to the// methods have been defined in the VERA testbench.// Check that no errors have occuredif ( model_1.showStatus() == FLEX_VERA_FATAL ||model_2.showStatus() == FLEX_VERA_FATAL ) {}// Errors exist, take suitable actionfork{// Send commands to the FlexModel Instance 1// Note that the id is encapsulated in the model// class and thus is not an argument to the commands.model_1.write(address1, data1, ‘FLEX_WAIT_F, status);model_1.write(address2, data2, ‘FLEX_WAIT_F, status);model_1.write(address3, data3, ‘FLEX_WAIT_F, status);October 6, 2003 Synopsys, Inc. 211