Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models9Using VERA with Synopsys ModelsOverviewVERA is a testbench automation tool that works as a front-end to Verilog or VHDLsimulators. For general information on VERA, refer to:http://www.synopsys.com/products/veraThe procedures in this chapter are organized into the following major sections:● “Using VERA with FlexModels” on page 207● “Using VERA with DesignWare Memory Models” on page 223Using VERA with FlexModelsThis section explains how to use VERA with FlexModels, including a special section onhow to use VERA and VCS with FlexModels. This information is presented in thefollowing sections:● “Using FlexModels with the VERA UDF Interface” on page 208● “Creating a VERA Testbench” on page 210● “VERA Testbench Example” on page 211● “Incorporating FlexModels in a VERA Testbench” on page 213● “Using VERA with FlexModels and VCS” on page 215October 6, 2003 Synopsys, Inc. 207