Simulator Configuration Guide for Synopsys Models

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Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration GuideScirocco Template Generator Script for Hardware ModelsHere is the nawk script that you can use to generate VHDL wrappers for the hardwaremodels. Because of the length this script, you will have to cut-and-paste one page at atime from this PDF file to get the whole thing copied to your environment.********************************************# In your design directory type:## nawk -f hwm2vhdl.nawk $HWM/.NAM > .vhd## (where "$HWM" is the full path to your hardware modeling directory)# Instantiate .vhd into your design.## THE SCRIPT:## Script to generate a VSS/Scirocco VHDL shell for a hardware model# using the .NAM fileBEGIN {pin_type = 0is_it_a_vector = "No"data_type = ""prev_signal = ""prev_test = ""prev_number = ""prev_dir = ""ending = ";"}printf "library SYNOPSYS;\n"printf " use SYNOPSYS.ATTRIBUTES.all;\n"printf "library IEEE;\n"printf " use IEEE.std_logic_1164.all;\n\n"$2 ~ /generic_device_name/ {device = $3printf "entity " device " is\n"printf " generic\n"printf " (\n"printf " timing : LMSI_TIMING_MEASUREMENT := DISABLED;\n"printf " delay_type : LMSI_DELAY_TYPE := TYPICAL;\n"printf " delay : LMSI_DELAY := ENABLED;\n"printf " log : LMSI_LOG := DISABLED;\n"printf " timing_violations : LMSI_TIMING_VIOLATIONS := DISABLED;\n"printf " xprop : LMSI_XPROP := DISABLED;\n"printf " xprop_method : LMSI_XPROP_METHOD := HIGH\n"printf " );\n\n"printf " port\n"printf " (\n"}$4 ~ /$in_pin$/ || $4 ~ /$out_pin$/ || $4 ~ /$io_pin$/ \|| $4 ~ /$power_pin$/ {pin_type++}204 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys Models$2 ~ /\=/ || ($0 ~ /^$/ && pin_type ~ /3/) {if (pin_type == 1) {direction = "in "}else if (pin_type == 2) {direction = "out "}else if (pin_type == 3) {direction = "inout"}else {next}current_signal = $1 " "gsub(/\{/, "", current_signal)gsub(/\'/, "", current_signal)}current_test = current_signalgsub(/[0-9]+ /, " ", current_test)n = split(current_signal, array_a, "[a-zA-Z]")current_number = array_a[n]gsub(/ /, "", current_number)if (prev_signal ~ /[0-9]+ /) {if (current_test == prev_test) {if (is_it_a_vector == "No") {data_start = prev_number}if ((current_number == prev_number - 1) || (current_number == prev_number + 1)){is_it_a_vector = "Yes"}prev_signal = current_signalprev_test = current_testprev_number = current_numbernext}else {if (is_it_a_vector == "Yes") {total = prev_number + data_startif (prev_number > data_start) {data_end = data_startdata_start = prev_number}else {data_end = prev_number}data_type = "_vector (" data_start " " "downto " data_end ")"prev_signal = prev_test}}}if (prev_signal != "") {gsub(/ /, "", prev_signal)n = split(prev_signal, array_c, "[a-zA-z0-9_]")y = 20 - nif (y > 0) {for (i = 1; i
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 7: Using QuickSim II with S
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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