Simulator Configuration Guide for Synopsys Models

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide7. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement for the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;8. Instantiate FlexModels in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thesupplied bit-blasted wrapper (model_fx_vss.vhd).Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );9. Compile your testbench as shown in the following example:% vhdlan testbench10. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim -vhpi slm_vhpi:foreignINITelab:cpipeb. If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe design198 Synopsys, Inc. October 6, 2003