Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsTable 28: FlexModel Scirocco VHDL Files (Continued)File Name Description Locationmodel.vhdmodel_tst.vhdA bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench. This file assumes thatthe “COMPONENTS” package has beeninstalled in the logical library “slm_lib”.A testbench that instantiates the model andshows how to use basic model commands.workdir/examples/vhdl/workdir/examples/vhdl/4. Update the clock frequency supplied in the model_user_pkg.vhd file in yourworking directory to correspond to the desired clock period for the model. After yourun flexm_setup this file is located in:workdir/src/vhdl/model_user_pkg.vhdwhere workdir is your working directory.5. Add the following line to your .synopsys_vss.setup file:SLM_LIB : SLM_LIB_PATHTIMEBASE = PS6. Compile the FlexModel VHDL files into logical library slm_lib as follows:NoteThese examples provide details for event-based simulation. For informationon cycle-based operation, refer to the Scirocco Reference Manual.% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/flexmodel_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_user_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_fx_comp.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_fx_vss.vhd% vhdlan -w slm_lib workdir/src/vhdl/model.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.October 6, 2003 Synopsys, Inc. 197