Simulator Configuration Guide for Synopsys Models

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Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide8. Add the following line to your synopsys_sim.setup file:TIMEBASE = PS9. Instantiate SmartModels in your VHDL design. For information on requiredconfiguration parameters and instantiation examples, refer to “Using SmartModelswith SWIFT Simulators” on page 18.10. Compile your testbench as shown in the following example:% vhdlan testbench11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim designb. If you are using Scirocco 2000.12:% scsim designFor more information, refer to the Scirocco Reference Manual.create_smartmodel_lib Command ReferenceThe command reference for create_smarmodel_lib is as follows:Syntaxcreate_smartmodel_lib [--] [-nc] [-create] [-srcdir dirpath] [-analyze] [-nowarn][-modelfile file] {-model model_name}Arguments-- Displays the usage message and lists the command lineoptions.-nc-create-src_dir dirpathSuppresses the Synopsys copyright message.Creates the VHDL source files (.vhd files) for theSMARTMODEL library and saves the source files in the$LMC_HOME/synopsys directory.Lets you specify the location of the VHDL source files thatyou create. The default location is $LMC_HOME/synopsys.194 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys Models-analyze-nowarn-modelfile file-model model_nameAnalyzes the SMARTMODEL library source files (.vhd files)by invoking vhdlan. The analyzed files (.sim and .mra files)are saved in the $LMC_HOME/synopsys/smartmodeldirectory. This directory is specified by SMARTMODELlogical name mapping in the setup file.Suppresses the generation of warning messages that notifyyou of any port name mappings.A list of SMARTMODEL component names is read from file.Names are separated by spaces. Only the specified componentnames are included in the SMARTMODEL componentlibrary.The model_name is included in the resulting SMARTMODELcomponent library. Repeat this option to specify multiplemodels. Only specified component names are included in theSMARTMODEL component library.DescriptionWhen issued without options, the create_smartmodel_lib command takes all of the filesin the $LMC_HOME/models directory, creates and analyzes the VHDL template files,and saves them in the $LMC_HOME/synopsys/smartmodel directory. If you do nothave write permission for $LMC_HOME/synopsys/smartmodel, the commandterminates with an error message. In that case, you must use the -src_dir option tospecify a writable directory in which to place the VHDL templates. You must alsospecify that directory through the SMARTMODEL library mapping in the.synopsys_vss.setup file in your current working directory.October 6, 2003 Synopsys, Inc. 195
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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Simulator Configuration Guide for Synopsys Models

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