Simulator Configuration Guide for Synopsys Models

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide8. Add the following line to your synopsys_sim.setup file:TIMEBASE = PS9. Instantiate SmartModels in your VHDL design. For information on requiredconfiguration parameters and instantiation examples, refer to “Using SmartModelswith SWIFT Simulators” on page 18.10. Compile your testbench as shown in the following example:% vhdlan testbench11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim designb. If you are using Scirocco 2000.12:% scsim designFor more information, refer to the Scirocco Reference Manual.create_smartmodel_lib Command ReferenceThe command reference for create_smarmodel_lib is as follows:Syntaxcreate_smartmodel_lib [--] [-nc] [-create] [-srcdir dirpath] [-analyze] [-nowarn][-modelfile file] {-model model_name}Arguments-- Displays the usage message and lists the command lineoptions.-nc-create-src_dir dirpathSuppresses the Synopsys copyright message.Creates the VHDL source files (.vhd files) for theSMARTMODEL library and saves the source files in the$LMC_HOME/synopsys directory.Lets you specify the location of the VHDL source files thatyou create. The default location is $LMC_HOME/synopsys.194 Synopsys, Inc. October 6, 2003