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Simulator Configuration Guide for Synopsys Models

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<strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Chapter 8: Using Scirocco with <strong>Synopsys</strong> <strong>Models</strong>Using Smart<strong>Models</strong> with SciroccoTo use Smart<strong>Models</strong> with Scirocco, follow this procedure:1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. To create SmartModel VHDL templates, check to see if you have write permission<strong>for</strong> $LMC_HOME/synopsys/smartmodel; if so skip to Step 5. Otherwise, open thesynopsys_sim.setup file in your current working directory and search <strong>for</strong> the stringSMARTMODEL. By default, the logical library name SMARTMODEL is mappedto $LMC_HOME/synopsys/smartmodel, as follows:SMARTMODEL : $LMC_HOME/synopsys/smartmodel3. Change the directory to one where you have write permissions, as shown in thefollowing example:SMARTMODEL : ~/smartmodel4. Generate a VHDL model wrapper file <strong>for</strong> the model by invokingcreate_smartmodel_lib with any optional arguments. For complete in<strong>for</strong>mation onthe syntax <strong>for</strong> this command, refer to “create_smartmodel_lib CommandReference” on page 194.% $SYNOPSYS_SIM/sim/bin/create_smartmodel_lib arguments5. If you changed the SMARTMODEL mapping in Step 3, you must use the -srcdiroption to specify that directory. Also, you can save time by using the -model or-modelfile option to specify the models you want. Otherwise, the script processes allinstalled Smart<strong>Models</strong>. For example, here is a recommended set of options to use<strong>for</strong> one SmartModel (ttl00 in this example):% $SYNOPSYS_SIM/sim/bin/create_smartmodel_lib -model ttl00 \-srcdir ~/smartmodel6. After create_smartmodel_lib finishes executing, verify that the VHDL templatefiles were created in the appropriate directory.7. To use Smart<strong>Models</strong> in the VHDL source file of your design, specify theSMARTMODEL library and instantiate each SmartModel component. In the VHDLdesign file that uses SmartModel components, enter the following library and useclauses:library SMARTMODEL;use SMARTMODEL.components.allThe library logical name SMARTMODEL must be mapped to appropriatedirectories in your synopsys_sim.setup file.October 6, 2003 <strong>Synopsys</strong>, Inc. 193

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