Simulator Configuration Guide for Synopsys Models

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.Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideVerifying the Technology FileDuring registration, lm_model calls the tmg_to_ts converter. This converter extractstiming information from the following Shell Software files to create a Technology File:●●●●Variable declarations (.DCL) fileTiming checks (.TCK) fileState tracking (.TRK) fileDelays (.DLY) file● Force values (.FRC) fileThe technology file specifies propagation delays and some timing checks, as well astechnology-dependent data for the simulation model. Table 26 shows how ShellSoftware timing statements are converted into technology file statements.NoteMany Shell Software statements have no technology file equivalents. Thetmg_to_ts converter includes each “untranslatable” statement in thetechnology file as a comment and/or generates a warning message. For thisreason, we recommend that you use the Shell Software timing files insteadof the technology file during simulation. For instructions, refer to “TimingShell Selection” on page 179.Table 26: Shell Software to Technology File ConversionShell Software Statementscycle_time input_state (storage_pin) =timing_specTechnology File StatementsfMIN = min_freq on storage_pin (input_trans)fMAX = max_freq on storage_pin (input_trans)decrement name —default_delay timing_specdelay from input_state (eval_storage_pin) tooutput_state (output_pin) = timing_spectP = timing_spec on eval_storage_pin(input_trans) to output_pin (output_trans)tP = timing_spec on eval_storage_pin(input_trans) to output_pin (output_trans)force_value output_pin = pin_value —hold after input_state 1 (storage_pin) ofinput_state 2 (input_pin) = timing_spectH = timing_spec on input_pin (input_state 2 ) tostorage_pin (input_trans 1 )174 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTable 26: Shell Software to Technology File Conversion (Continued)Shell Software StatementsTechnology File Statementsif (condition) {statements}else_if (condition) {statements}else {statements}end_if—increment name —print (severity, arguments) —pulse_width input_state (storage_pin) = timing_specrecovery after (condition)during (condition)before input_state(storage_pin) =timing_specelse_during (condition)before input_state(storage_pin) =timing_specelsebefore input_state(storage_pin) =timing_specend_duringtW = timing_spec on storage_pin (input_state)No equivalent to maximum pulse width time.—set name = value —setup before input_state 1 (storage_pin) ofinput_state 2 (input_pin) = timing_specstable valid (input_pin) while (store_pin =input_state)tS = timing_spec on input_pin (input_state 2 ) tostorage_pin (input_trans 1 )tSTAB = 0 : 0 on input_pin (V) to store_pin (trans1,trans2)var enumerated_list name = identifier —var counter name = number —when (condition) {statements}else_when (condition) {statements}else {statements}end_whenwith conditionNo equivalents to else_when and else clausesOctober 6, 2003 Synopsys, Inc. 175
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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