Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models// tmg_to_ts v8.5_2.1 Sat Oct 19 20:18:24 PDT 1996// Falcon Framework v8.5_2.5 Thu May 30 17:31:43 PDT 1996//// Copyright (c) Mentor Graphics Corporation, 1982-1995, All Rights Reserved.// UNPUBLISHED, LICENSED SOFTWARE.// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.//// Mentor Graphics software executing under Sun SPARC SunOS.//// TC - The Technology Compiler v8.5_2.2 Sat Jun 22 10:56:50 PDT 1996// Falcon Framework v8.5_2.5 Thu May 30 17:31:43 PDT 1996//// Copyright (c) Mentor Graphics Corporation, 1982-1995, All Rights Reserved.// UNPUBLISHED, LICENSED SOFTWARE.// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.//// Mentor Graphics software executing under Sun SPARC SunOS.////// Note: lm_model completed successfullyEditing the SymbolDuring registration, the lm_model utility reads the Shell Software to determine thedevice’s input, output, and I/O pin names. The utility then flattens all buses to individualbits and generates a Mentor Graphics Design Architect script that creates the symbol.The process uses the following rules to create the symbol:● All input pins are placed starting in the lower left corner and proceeding upwards.●●●●All output pins are placed starting in the lower right corner and proceeding upwards.I/O pins are placed for minimizing the symbol’s height.All buses are grouped with the least significant bit placed lower on the symbol thanthe most significant bit.A single grid spacing is left between buses, grouped scalar pins, input and I/O pins,and output and I/O pins.Since symbol standards vary, you may need to use the Symbol Editor in DesignArchitect to modify the appearance of the automatically-generated symbol. For moreinformation, refer to your Design Architect documentation.October 6, 2003 Synopsys, Inc. 173