Simulator Configuration Guide for Synopsys Models

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Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideExample of a pin_map FileThe following example pin_map file customizes the standard symbol supplied with themodel of the National Semiconductor DP8429 DRAM controller shown in Figure 4.Figure 4: National Semiconductor DP8429 DRAM ControllerIn the example pin_map file shown below, the names that are changed on the firstsymbol are labeled CS, RASIN, R/C, CASIN, WIN, RA, RB, RC, RD, and M2. Theywill have an “L” added to the name to denote that they are asserted low. Notice that abus has been defined for each of these sets of pins: Q0 through Q9, R0 through R9, C0through C9, and B0 through B1.## DP8429 PIN NAME CHANGES#IN CSL = CS ;IN RASINL = RASIN ;IN CASINL = CASIN ;IN RCL = R/C ;IN WINL = WIN ;IN RFSH = M2 ;IN R = R9 R8 R7 R6 R5 R4 R3 R2 R1 R0;148 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsIN C = C9 C8 C7 C6 C5 C4 C3 C2 C1 C0;IN B = B1 B0;OUT WEL = WE ;OUT RAL = RAS3 ;OUT RBL = RAS2 ;OUT RCL = RAS1 ;OUT RDL = RAS0 ;OUT Q = Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0;Conditional Pin MappingUse a conditional clause in the pin_map file to cause the model to use different parts ofa pin_map file based on the value of a certain property. The syntax is:% property_name property_valueThis method is used by the models to map the pins from the BUS symbols to the model.The pin map parser searches for the property_name in the design database and thencompares the property_value. If the property is not present, or if the actual value of theproperty does not match the property_value exactly, everything in the file until the nextpercent sign (%) is ignored.The following example shows the pin_map file that provides mapping from the pin tothe bus symbols for the Logic Devices LSH32 32-bit barrel shifter.## Bus Package for the LSH32#% PKG BUSIN I = I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 ;OUT Y = Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ;IN SI = SI4 SI3 SI2 SI1 SI0 ;OUT SO = SO4 SO3 SO2 SO1 SO0October 6, 2003 Synopsys, Inc. 149
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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ContentsSimulator Configuration Gui
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FiguresSimulator Configuration Guid
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TablesSimulator Configuration Guide
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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Simulator Configuration Guide for Synopsys Models

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