Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys Models2. Run ncvhdl to compile your .vhd files, as shown in the following example:% ncvhdl TILS299.vhd TILS299_comp.vhd TB_TILS299.vhd3. Elaborate the design, as shown in the following example:% ncelab -messages work.tb_tils299:test4. Invoke the NC-VHDL simulator, as shown in the following example:% ncsim -gui work.tb_tils299:testNC-VHDL UtilitiesThe following hardware modeler simulator commands are supported in NC-VHDL:lm_log_test_vectors (“instance_name”, 1/0, “filename”);Enables (1) or disables (0) vector logging for hardware models.lm_timing_measurements (“instance_name”, 1/0, “filename”);Enables (1) or disables (0) timing measurements for hardware models.lm_enable_timing_checks ([device_name(s)....])Enables timing checks for hardware models.lm_disable_timing_checks ([device_name(s)....])Disables timing checks for hardware models.lm_unknowns (“option=value”, ....device_or_pin);Determines how unknown values are handled by hardware models. Supported optionsinclude:●●●●propagate=yes/novalue=previous/high/lowsequence_count=0-20random_seed=0-65535● device_or_pinlm_loop_instance ([instance_name]);Makes the hardware modeler enter loop mode, where it continually replays the patternhistory of the specified instance.lm_pam_shortage(“actions=save/sleep/finish/free/suspend/drop_faults”,”sleep_minutes=n, “sleep_count=n”, “save_file=filename”);October 6, 2003 Synopsys, Inc. 121