Simulator Configuration Guide for Synopsys Models

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide12. Set the LMC_TIMEUNIT environment variable to -12 for 1 ps resolution, as shownin the following example:% setenv LMC_TIMEUNIT -12This sets a global timing resolution for all SWIFT models in your simulation. Formore information on the LMC_TIMEUNIT environment variable, refer to theCadence documentation for NC-VHDL.13. Invoke the NC-VHDL simulator as shown in the following example:% ncsim designUsing DesignWare Memory Models withNC-VHDLDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx).To use DWMM models with NC-VHDL, follow these steps:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. Edit your cds.lib file to specify the logical library slm_lib for DWMM models:DEFINE slm_lib ./slm_libNoteAlso, make sure your cds.lib and hdl.var files contain the correctSOFTINCLUDE statements for running NC-VHDL.3. Create a directory named slm_lib:mkdir slm_lib4. Compile the required Synopsys libraries into the slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhdNoteIgnore the warning: ncvhdl_p: *W,FATSPB (slm_hdlc.vhd,72).% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd114 Synopsys, Inc. October 6, 2003