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Simulator Configuration Guide for Synopsys Models

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<strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Chapter 6: Using NC-VHDL with <strong>Synopsys</strong> <strong>Models</strong>8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement <strong>for</strong> the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;9. Instantiate Flex<strong>Models</strong> in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thebit-blasted wrapper generated in Step 3 (model_fx.vhd) using ncshell.Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );10. Compile the FlexModel VHDL files into logical library slm_lib as follows:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhd% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/flexmodel_pkg.vhd% ncvhdl -w slm_lib workdir/src/vhdl/model_user_pkg.vhd% ncvhdl -w slm_lib workdir/src/vhdl/model_pkg.vhd% ncvhdl -w slm_lib workdir/examples/vhdl/model_fx_comp.vhd% ncvhdl -w slm_lib model_fx.vhd% ncvhdl -w slm_lib workdir/examples/vhdl/model.vhd% ncvhdl-w work testbench11. Elaborate your design as shown in the following example:% ncelab cfgtestOctober 6, 2003 <strong>Synopsys</strong>, Inc. 113

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