Simulator Configuration Guide for Synopsys Models

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide6. Compile the other VHDL files into the work library, as shown in the followingexample:% ncvhdl -w work testbench.vhd7. Elaborate your design as shown in the following example:% ncelab cfgtest8. Set the LMC_TIMEUNIT environment variable to -12 for 1 ps resolution, as shownin the following example:% setenv LMC_TIMEUNIT -12This sets a global timing resolution for all SWIFT models in your simulation. Formore information on the LMC_TIMEUNIT environment variable, refer to theCadence documentation for NC-VHDL.9. Invoke the NC-VHDL simulator on your design as shown in the following example:% ncsim designUsing FlexModels with NC-VHDLTo use FlexModels with NC-VHDL, follow this procedures:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. If you have built your own Foreign Model Interface (FMI) shared library or youhave another third party FMI, perform this step.AttentionIf you do not build your own FMI library, skip to Step 3.NC-VHDL binds in only one shared FMI library at runtime. If your design usesFMI, you need to build a new FMI shared library that contains your library and theFlexModel library. A FlexModel archive library can be found at:HP-UX 32 and 64 bits:$LMC_HOME/lib/hp700.lib/libfmi_ar.a$LMC_HOME/lib/hp64.lib/libfmi_ar.aSolaris 32 and 64 bits:$LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.a$LMC_HOME/lib/sparc64.lib/libfmi_ar.a110 Synopsys, Inc. October 6, 2003