Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys Models6Using NC-VHDL with SynopsysModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with NC-VHDL. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 107● “Using SmartModels with NC-VHDL” on page 109● “Using FlexModels with NC-VHDL” on page 110● “Using DesignWare Memory Models with NC-VHDL” on page 114● “Using Hardware Models with NC-VHDL” on page 120NoteCadence’s NC-VHDL simulator does not support on any platform C-Flexbased FlexModels when the control language is Vera. Cadence is aware ofthe problem and plans a future fix.Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases the procedures that follow in this chapter include steps forsetting additional environment variables.October 6, 2003 Synopsys, Inc. 107