Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models$lm_timing_information Command ReferenceThe $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance.Syntax$lm_timing_information (“instance_path”, “timing_option”);Argumentsinstance_pathtiming_optionSpecifies the Verilog pathname of the instance whose timinginformation is to be modified.Allowed values are “nodelay” to ignore all delay information,“delay” to process all delay information, “notimingchecks” toignore all timing checks, and “timingchecks” to apply alltiming checks. The defaults are “delay” and “timingchecks”.DescriptionThe $lm_timing_information command allows you to override the hardware modeler’sdefault handling of timing information for a specified model instance. By default, thehardware modeler processes all delay information and applies all timing checks. Youcan decrease model evaluation time by disabling these activities. The hardware modelerdoes not process information that is not needed by the simulator.ExampleThe following example disables timing checks for the “U1” model instance.$lm_timing_information (“U1”, “notimingchecks”);October 6, 2003 Synopsys, Inc. 101