Simulator Configuration Guide for Synopsys Models

More documents

Recommendations

Info

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide$lm_loop_instance Command ReferenceThe $lm_loop_instance command enables the loop mode for a specified model instance.Syntax$lm_loop_instance (“instance_path”)Argumentsinstance_pathSpecifies the pathname of the model instance for which theloop mode is to be enabled.DescriptionEnables the loop mode for a specified instance. In loop mode, the hardware modelerrepeatedly plays to the physical device the pattern history of the specified deviceinstance. This command is most often used to analyze the behavior of a device and itspattern history with an oscilloscope or logic analyzer connected to the device.Once in loop mode, the interface prompts you to press the Return key to exit the loopmode.ExamplesThe following example turns on loop mode for the “U1” model instance.$lm_loop_instance ( “U1” );The following message is displayed while the instance is in loop mode.Entering loop mode for hardware model instance U1Press Return to terminate loop mode.100 Synopsys, Inc. October 6, 2003
Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models$lm_timing_information Command ReferenceThe $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance.Syntax$lm_timing_information (“instance_path”, “timing_option”);Argumentsinstance_pathtiming_optionSpecifies the Verilog pathname of the instance whose timinginformation is to be modified.Allowed values are “nodelay” to ignore all delay information,“delay” to process all delay information, “notimingchecks” toignore all timing checks, and “timingchecks” to apply alltiming checks. The defaults are “delay” and “timingchecks”.DescriptionThe $lm_timing_information command allows you to override the hardware modeler’sdefault handling of timing information for a specified model instance. By default, thehardware modeler processes all delay information and applies all timing checks. Youcan decrease model evaluation time by disabling these activities. The hardware modelerdoes not process information that is not needed by the simulator.ExampleThe following example disables timing checks for the “U1” model instance.$lm_timing_information (“U1”, “notimingchecks”);October 6, 2003 Synopsys, Inc. 101
Page 1:
Simulator ConfigurationGuide for Sy
Page 4 and 5:
ContentsSimulator Configuration Gui
Page 6 and 7:
ContentsSimulator Configuration Gui
Page 8 and 9:
FiguresSimulator Configuration Guid
Page 10 and 11:
TablesSimulator Configuration Guide
Page 12 and 13:
PrefaceSimulator Configuration Guid
Page 14 and 15:
Page 16 and 17:
Page 18 and 19:
Chapter 1: Using Synopsys Models wi
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Chapter 2: Using VCS with Synopsys
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51: Chapter 2: Using VCS with Synopsys
Page 60 and 61: Chapter 3: Using ModelSim Verilog w
Page 74 and 75: Chapter 4: Using ModelSim VHDL with
Page 90 and 91: Chapter 5: Using NC-Verilog with Sy
Page 108 and 109: Chapter 6: Using NC-VHDL with Synop
Page 124 and 125: Chapter 7: Using QuickSim II with S
Page 150 and 151:
Chapter 7: Using QuickSim II with S
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
.Chapter 7: Using QuickSim II with
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Chapter 8: Using Scirocco with Syno
Page 194 and 195:
Page 196 and 197:
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Chapter 9: Using VERA with Synopsys
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Chapter 10: Using SystemC with Syno
Page 264 and 265:
Page 266 and 267:
Page 268 and 269:
Appendix A: Using LMTV with Synopsy
Page 270 and 271:
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Appendix B: Using Custom Memory Mod
Page 284 and 285:
Page 286 and 287:
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Page 296 and 297:
Page 298 and 299:
Page 300 and 301:
Page 302 and 303:
IndexSimulator Configuration Guide$
Page 304 and 305:
IndexSimulator Configuration Guidef
Page 306 and 307:
IndexSimulator Configuration GuideL
Page 308 and 309:
IndexSimulator Configuration GuideQ
Page 310 and 311:
IndexSimulator Configuration GuideS
show all

Simulator Configuration Guide for Synopsys Models

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?