Simulator Configuration Guide for Synopsys Models

Simulator ConfigurationGuide for Synopsys ModelsTo search the entire manualset, press this toolbar button.For help, refer to intro.pdf.October 6, 2003

Simulator Configuration GuideContentsContentsPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Typographical and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Comments? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Chapter 1Using Synopsys Models with Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17About the Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Using SmartModels with SWIFT Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18SmartModel SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Instantiating SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20The SWIFT Command Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Fault Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Using FlexModels with SWIFT Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23flexm_setup Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Instantiating FlexModels with C-only Command Mode . . . . . . . . . . . . . . . . . . 26Using DesignWare Memory Models with SWIFT Simulators . . . . . . . . . . . . . . . . 29DesignWare Memory Model SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . 29Instantiating DesignWare Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Using Hardware Models with Different Simulators . . . . . . . . . . . . . . . . . . . . . . . . 37Linking Other Supported Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Supporting 32-bit Libraries on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Chapter 2Using VCS with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Supporting 32-Bit Libraries on 64-Bit Platforms . . . . . . . . . . . . . . . . . . . . . . . 41Using SmartModels with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Using FlexModels with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44VCS FlexModel Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48October 6, 2003 Synopsys, Inc. 3

ContentsSimulator Configuration GuideScript for Running FlexModel Examples in VCS . . . . . . . . . . . . . . . . . . . . . . . 51Example Simulator Run Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Using DesignWare Memory Models with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Using Hardware Models with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Example Using Runtime Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Example Using DelayRange Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57VCS Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Chapter 3Using ModelSim Verilog with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Using SmartModels with ModelSim Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Using FlexModels with ModelSim Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Using DesignWare Memory Models with ModelSim Verilog . . . . . . . . . . . . . . . . 66Using Hardware Models with ModelSim Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 68ModelSim Verilog Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Chapter 4Using ModelSim VHDL with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Using SmartModels with ModelSim VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75sm_entity Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Using FlexModels with ModelSim VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Using DesignWare Memory Models with ModelSim VHDL . . . . . . . . . . . . . . . . . 82Using Hardware Models with ModelSim VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . 84ModelSim VHDL Example Using TILS299 Hardware Model . . . . . . . . . . . . . 85hm_entity Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86ModelSim VHDL Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Chapter 5Using NC-Verilog with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Using SmartModels with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Using FlexModels with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Using DesignWare Memory Models with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . 954 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideContentsUsing Hardware Models with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97NC-Verilog Utilities Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98NC-Verilog Utilities Reference Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99$lm_log_test_vectors Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 99$lm_loop_instance Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100$lm_timing_information Command Reference . . . . . . . . . . . . . . . . . . . . . . . . 101$lm_timing_measurements Command Reference . . . . . . . . . . . . . . . . . . . . . . 102$lm_unknowns Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103lmvsg Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Chapter 6Using NC-VHDL with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 109Using SmartModels with NC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Using FlexModels with NC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Using DesignWare Memory Models withNC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Using VERA and DesignWare Memory Models withNC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Using Hardware Models with NC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120NC-VHDL Example with TILS299 Hardware Model . . . . . . . . . . . . . . . . . . 120NC-VHDL Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Chapter 7Using QuickSim II with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 124Using SmartModels and FlexModels with QuickSim II . . . . . . . . . . . . . . . . . . . . 125Installing the QuickSim II SWIFT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 125Using SmartModels/FlexModels with QuickSim II . . . . . . . . . . . . . . . . . . . . 127Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Custom Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Using DesignWare Memory Models with QuickSim II . . . . . . . . . . . . . . . . . . . . 151Installing the QuickSim II SWIFT Interface for DWMM . . . . . . . . . . . . . . . . 151DWMM Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151DWMM Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158DWMM Custom Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163October 6, 2003 Synopsys, Inc. 5

ContentsSimulator Configuration GuideUsing Hardware Models with QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Setting up Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . 164Using Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166Model Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Registering a Model with lm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171Modifying a Hardware Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Simulating with Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . 177lm_model Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185tmg_to_ts Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Chapter 8Using Scirocco with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 192Using SmartModels with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193create_smartmodel_lib Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . 194Using FlexModels with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Using DesignWare Memory Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . 199Using Hardware Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Scirocco Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202VHDL Model Generics with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Chapter 9Using VERA with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Using VERA with FlexModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Using FlexModels with the VERA UDF Interface . . . . . . . . . . . . . . . . . . . . . 208Creating a VERA Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210VERA Testbench Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Incorporating FlexModels in a VERA Testbench . . . . . . . . . . . . . . . . . . . . . . 213Using VERA with FlexModels and VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Example Vera System Testbenches For FlexModels . . . . . . . . . . . . . . . . . . . . 218Using VERA with DesignWare Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . 223DesignWare Memory Models with VERA . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Adding DesignWare Memory Model Commands to the VERA Testbench . . 230Building the VERA UDF Dynamic Library . . . . . . . . . . . . . . . . . . . . . . . . . . 235Compiling the VERA Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242Creating a VERA List File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Building and Invoking the Simulator Executable . . . . . . . . . . . . . . . . . . . . . . 2446 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideContentsChapter 10Using SystemC with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Using SmartModels with SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Using DesignWare Memory Models with SystemC . . . . . . . . . . . . . . . . . . . . . . . 264Appendix AUsing LMTV with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267What is LMTV? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Static Linking with LMTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Edited veriuser.c File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268LMTV Command-Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270LMTV Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271$lm_command() or $lai_command() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272$lm_dump_file() or $lai_dump_file() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273$lm_help() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274$lm_load_file() or $lai_load_file() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275$lm_monitor_enable() or $lai_enable_monitor() . . . . . . . . . . . . . . . . . . . . . . 276$lm_monitor_disable() or $lai_disable_monitor() . . . . . . . . . . . . . . . . . . . . . 276$lm_monitor_vec_map() and $lm_monitor_vec_unmap() . . . . . . . . . . . . . . . 278$lm_status() or $lai_status() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Appendix BUsing Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281Configuring Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282Controlling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Instantiating Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285Using Custom Memory Models with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286Using Custom Memory Models with VCS and Verilog Testbenches . . . . . . . 286Using Custom Memory Models with VCS and C Testbenches . . . . . . . . . . . . 287Using Custom Memory Models with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . 289Using Custom Memory Models with MTI Verilog . . . . . . . . . . . . . . . . . . . . . . . . 290Using Custom Memory Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . 292Using Custom Memory Models with MTI VHDL . . . . . . . . . . . . . . . . . . . . . . . . 294Using Custom Memory Models with NC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 296Using Custom Memory Models with VERA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301October 6, 2003 Synopsys, Inc. 7

FiguresSimulator Configuration GuideFiguresFigure 1: run_flex_examples_in_vcs.pl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 2: Sample Pin and Bus Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Figure 3: Visible Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 4: National Semiconductor DP8429 DRAM Controller . . . . . . . . . . . . . . . 148Figure 5: Bus and Pin Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 6: DWMM Visible Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Figure 7: Sample Component Interface for a Hardware Model . . . . . . . . . . . . . . . 168Figure 8: Hardware Model Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Figure 9: VERA Model Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Figure 10: DesignWare Memory Model with VERA Design Flow . . . . . . . . . . . . . 2298 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideTablesTablesTable 1: Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 2: SmartModel SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 3: FlexModel SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 4: FlexModel C-only Command Mode Files . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 5: DesignWare Memory Model SWIFT Parameters . . . . . . . . . . . . . . . . . . . . 29Table 6: VCS SmartModel Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 7: FlexModel VCS Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 8: VCS With One FlexModel On 32-bit Solaris Model Explanation . . . . . . . 49Table 9: FlexModel ModelSim Verilog File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 10: FlexModel MTI VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 11: FlexModel NC-Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 12: FlexModel NC-VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Table 13: Symbol Properties used by SWIFT Models . . . . . . . . . . . . . . . . . . . . . . . 129Table 14: Symbol Properties Required for Simulation . . . . . . . . . . . . . . . . . . . . . . . 130Table 15: Optional Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Table 16: Signal State Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 17: QuickSim II Command Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table 18: Elements in a TIBPAL22V10 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Table 19: Symbol Properties for DesignWare Memory Model Parameters . . . . . . . 153Table 20: Symbol Properties Required for DesignWare Memory Model Simulation 155Table 21: Optional DWMM Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Table 22: DWMM Signal State Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Table 23: Common Unsupported QuickSim II Commands . . . . . . . . . . . . . . . . . . . 160Table 24: Mentor Graphics Vendor CPU Operating System Suffixes . . . . . . . . . . . 165Table 25: Sample Component Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171Table 26: Shell Software to Technology File Conversion . . . . . . . . . . . . . . . . . . . . . 174Table 27: Signal Instance Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Table 28: FlexModel Scirocco VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Table 29: FlexModel Files Used with the VERA UDF Interface . . . . . . . . . . . . . . . 208Table 30: Link Line Object Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Table 31: VERA Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Table 32: FlexModel VERA Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Table 33: Key DesignWare Memory Model VERA Files . . . . . . . . . . . . . . . . . . . . 225Table 34: VERA List File Path Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Table 35: Valid Simultators for Using DWMM Models with VERA . . . . . . . . . . . . 244Table 36: Valid Platforms for Using DWMM Models with VERA . . . . . . . . . . . . . 244October 6, 2003 Synopsys, Inc. 9

TablesSimulator Configuration GuideTable 37: Simulators That Support Custom Memory Models . . . . . . . . . . . . . . . . . 281Table 38: Custom Memory Model Generic/Parameter Descriptions . . . . . . . . . . . . 282Table 39: Custom Memory Model Message Constants . . . . . . . . . . . . . . . . . . . . . . 284Table 40: VCS Custom Memory Model Explanation . . . . . . . . . . . . . . . . . . . . . . . . 28810 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidePrefacePrefaceAbout This ManualThis manual contains procedures for using Synopsys models with the most widely usedsimulators. The scope includes the following types of models:●●●●SmartModelsFlexModelsDesignWare Memory ModelsHardware ModelsNoteThis manual contains illustrations of third-party software files solely todemonstrate the end user modifications needed to get Synopsys modelsworking with these tools. Third-party software changes frequently. Refer tothe third-party tool vendor's documentation for definitive information abouttheir licensed software.Related DocumentsFor more information about SmartModels and FlexModels, or to navigate to a relatedonline document, refer to the Guide to SmartModel Documentation. For information onsupported platforms and simulators, refer to SmartModel Library Supported Simulatorsand Platforms.For detailed information about specific SmartModels (including FlexModels), use theBrowser tool ($LMC_HOME/bin/sl_browser) to access the online model datasheets.For more information about hardware models, or to navigate to a related onlinedocument, refer to the Guide to Hardware Model Documents.October 6, 2003 Synopsys, Inc. 11

PrefaceSimulator Configuration GuideManual OverviewThis manual contains the following chapters:PrefaceChapter 1Using Synopsys Models withSimulatorsChapter 2Using VCS with Synopsys ModelsChapter 3Using ModelSim Verilog withSynopsys ModelsChapter 4Using ModelSim VHDL withSynopsys ModelsChapter 5Using NC-Verilog withSynopsys ModelsChapter 6Using NC-VHDL with SynopsysModelsChapter 7Using QuickSim II with SynopsysModelsChapter 8Using Scirocco with SynopsysModelsChapter 9Using VERA with Synopsys ModelsChapter 10Using SystemC with SynopsysModelsDescribes the manual and lists the typographicalconventions and symbols used in it. Tells how to gettechnical assistance.Basic information for configuring and instantiatingSmartModels, FlexModels, DesignWare MemoryModels, and hardware models for use in varioussimulators.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with VCS. Includes a script that you can useto run FlexModel example testbenches in VCS.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with ModelSim Verilog.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with ModelSim VHDL.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with NC-Verilog.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with NC-VHDL.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with QuickSim II.How to configure SmartModels, FlexModels,DesignWare Memory Models, and hardware modelsfor use with Scirocco. Includes a script that you canuse to run FlexModel example testbenches inScirocco.How to configure FlexModels and DesignWareMemory Models for use with Vera.How to configure SmartModels and DesignWareMemory Models for use with SystemC.12 Synopsys, Inc. April 2002

Simulator Configuration GuidePrefaceAppendix AUsing LMTV with SynopsysModelsAppendix BUsing Custom Memory ModelsReference information for LMTV commands usedwith SmartModels, FlexModels, and DesignWareMemory Models on NC-Verilog, and ModelSimVerilog. Also includes static linking procedures forLMTV.How to create and use custom memory models.October 6, 2003 Synopsys, Inc. 13

PrefaceSimulator Configuration GuideTypographical and Symbol ConventionsThe following conventions are used throughout this document:Table 1: Documentation ConventionsConventionDescription and Example% Represents the UNIX prompt.BoldMonospaceItalic or ItalicUser input (text entered by the user).% cd $LMC_HOME/hdlSystem-generated text (prompts, messages, files, reports).No Mismatches: 66 Vectors processed: 66 Possible"Variables for which you supply a specific value. As a commandline example:% setenv LMC_HOME prod_dirIn body text:In the previous example, prod_dir is the directory where yourproduct must be installed.| (Vertical rule) Choice among alternatives, as in the following syntax example:-effort_level low | medium | high[ ] (Square brackets) Enclose optional parameters:pin1 [pin2 ... pinN]In this example, you must enter at least one pin name (pin1), butothers are optional ([pin2 … pinN]).TopMenu > SubMenuPulldown menu paths, such as:File > Save As …Getting HelpIf you have a question about using Synopsys products, please consult productdocumentation that is installed on your network or located at the root level of yourSynopsys product CD-ROM (if available). You can also access documentation forDesignWare products on the Web:●●Product documentation for many DesignWare products:http://www.synopsys.com/products/designware/docsDatasheets for individual DesignWare IP components:http://www.synopsys.com/products/designware/ipdir14 Synopsys, Inc. April 2002

Simulator Configuration GuidePrefaceYou can also contact the Synopsys Support Center in the following ways:●Open a call to your local support center using this Web page:http://www.synopsys.com/support/support.html●●Send an e-mail message to support_center@synopsys.com.Telephone your local support center:❍❍❍United States:Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific Time, Mon—Fri.Canada:Call 1-650-584-4200 from 7 AM to 5:30 PM Pacific Time, Mon—Fri.All other countries:Find other local support center telephone numbers at the following URL:http://www.synopsys.com/support/support_ctrAdditional InformationFor additional Synopsys DesignWare documentation, refer to the following page:http://www.synopsys.com/products/designware/docsFor up-to-date information about the latest implementation IP and verification models,visit the IP Directory:http://www.synopsys.com/products/designware/ipdirComments?To report errors in this document or make suggestions for improving it, please sende-mail to this address:doc@synopsys.comTo report an error that occurs on a specific page, copy the entire page (including headersand footers) to the body of your e-mail message. This will help us identify the source ofthe problem.October 6, 2003 Synopsys, Inc. 15

PrefaceSimulator Configuration Guide16 Synopsys, Inc. April 2002

Simulator Configuration GuideChapter 1: Using Synopsys Models with Simulators1Using Synopsys Models withSimulatorsOverviewSynopsys provides a variety of model types for the verification process. This chapterexplains the basic configuration steps for the following types that are not simulatorspecific,in the following major sections:● “Using SmartModels with SWIFT Simulators” on page 18● “Using FlexModels with SWIFT Simulators” on page 23● “Using DesignWare Memory Models with SWIFT Simulators” on page 29● “Using Hardware Models with Different Simulators” on page 37Later chapters in this manual contain simulator-specific procedures for using thedifferent model types.October 6, 2003 Synopsys, Inc. 17

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideAbout the ModelsSmartModels and FlexModels are binary behavioral models that connect to over 30commercial simulators through the SWIFT interface. If you are using a SWIFTsimulator that does not have a separate chapter devoted to it in this manual, refer to thischapter for the basic information needed to get the models working on your simulator.For information on SmartModel/FlexModel supported simulators, refer to theSmartModel Library Supported Platforms and Simulators Manual.DesignWare Memory Models are also binary behavioral models that support the SWIFTinterface. They can be used on several different popular simulators, all listed in thismanual.The hardware modeler uses real silicon in combination with specialized hardware andsoftware to represent the full functionality of modeled devices in your simulation. Itdoes not have a standard interface comparable to SWIFT. Hardware models are acombination of hardware and software, as follows:●The hardware consists of the actual silicon of the device being modeled, installed ona special-purpose Device Adapter and inserted into the hardware modeling system.● The software consists of a series of ASCII files containing Shell Software thatdescribes the device interface and initialization, along with optional informationsuch as timing delays, state tracking, and timing checks.For simulator-specific information about using hardware models, first see “UsingHardware Models with Different Simulators” on page 37 for an overview. Then consultthe appropriate simulator-specific chapter in this manual for detailed setup procedures.Using SmartModels with SWIFT SimulatorsSWIFT is a standard EDA event-level simulation interface developed by Synopsys. TheSWIFT interface enables multiple simulators with different requirements to use modelsfrom the same SmartModel Library. Each simulator provides a standard modelinterface that allows it to load the same SWIFT models.When the simulator encounters a SmartModel during simulation, it uses a set of SWIFTfunctions to create and configure the model, map to its ports, initialize it, and set its timeunits. The SWIFT interface also allows participating simulators to integrate theSmartModel Library into their particular framework, including application-specificmenus. For more information, refer to the documentation provided by your simulatorvendor.18 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsSmartModel SWIFT ParametersSmartModel attributes or parameters are model-specific values needed by the simulatorto configure a model. You configure SmartModels when you instantiate them in yourdesign using these SWIFT parameters. This could take the form of Verilog defparams,VHDL generics, or symbol properties, depending on the simulator you are using. Fordetails, refer to the documentation for your simulator.Table 2 lists the SmartModel configuration parameters. All SmartModels require anInstanceName, TimingVersion, and DelayRange. In addition, some SmartModels need aMemoryFile or PCLFile attribute. FlexModels use a slightly different set of attributesfor configuration, described in “FlexModel SWIFT Parameters” on page 23.Table 2: SmartModel SWIFT ParametersParameter Name Used By DescriptionInstanceName All SmartModels Specifies an instance namefor a particular instance of aSmartModel. Used inmessages to indicate whichinstance is issuing themessage; also used in userdefinedtiming. Can be setby the simulator from thehierarchical name in theHDL description; or can beset using the InstanceNameproperty on the symbol.TimingVersion All SmartModels Specifies the timing versiona SmartModel instanceshould use when schedulingchanges on its outputs orchecking setup and holdtimes on its inputs.DelayRange All SmartModels Specifies a propagationdelay range for a particularinstance of a SmartModel.The allowed values are“min”. “typ”, and “max.”MemoryFileSmartModels with internalmemory such as RAMs,ROMs, and processorsand controllers that haveon-chip RAM or ROM.Specifies a memory imagefile (MIF) to load for aparticular instance of aSmartModel.October 6, 2003 Synopsys, Inc. 19

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTable 2: SmartModel SWIFT Parameters (Continued)Parameter Name Used By DescriptionJEDECFilePCLFileJEDEC-based PAL andPLD modelsProcessor models (forexample, microprocessorsand microcontrollers);these are usually hardwareverification models.Specifies a JEDEC file toload for a particular instanceof a SmartModel.Specifies a compiled PCLprogram file to load for aparticular instance of aSmartModel.NoteTo determine the required configuration file for any SmartModel, refer tothe model’s datasheet.Instantiating SmartModelsIf you are using an HDL-based simulator, generate a model wrapper file (model.v ormodel.vhd) using your simulator vendor’s procedure. Use the model wrapper toinstantiate the model in your design. The model wrapper must map the model’s ports tosignals in your design. Modify SWIFT parameters in the model wrapper as needed. Hereare some parameter examples for a SmartModel memory model:VHDL:U1: cyc7150GENERIC MAP(TimingVersion => "cy7c150",DelayRange => "MAX",MemoryFile => "mem1";.... )Verilog:cyc7150 u1( ... );defparamu1.TimingVersion = "cy7c150",u1.DelayRange = "MAX",u1.MemoryFile = "mem1";You can also instantiate SmartModels in schematic-capture based systems by usingmodel symbols and attaching values to symbol properties. For details on instantiatingSmartModels using symbols with QuickSim II, refer to “Using QuickSim II withSynopsys Models” on page 123.20 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsThe SWIFT Command ChannelThe SWIFT interface specification requires that simulator vendors include a minimalcommand interface to the SmartModel Library. This interface is called the commandchannel. The command channel supports several types of commands:● “Model Commands” on page 21● “Session Commands” on page 21Model CommandsModel commands affect only a selected model instance. Following is a list of themodel commands:DumpMemory output_fileDumps the current memory image of a model to the specified output file. Ifoutput_file exists, it is overwritten; otherwise, a new file is created.ReportStatusPrints a message that describes the configuration status of a model.SetConstraints ON | OFFEnables or disables timing constraint checks for a model. By default, models checkfor and warn of timing constraints.NoteSome simulator vendors supply additional interfaces to the DumpMemory,ReportStatus, and SetConstraints capabilities.Session CommandsSession commands act on all models in the simulation session. You can enable sessioncommands by setting the LMC_COMMAND environment variable. Here is an examplethat enables tracing of timing files and model versions, followed by a list of all thesession commands.% setenv LMC_COMMAND "TraceTimeFile on;TracePath ON"NoteThe session command strings are case-insensitive, as illustrated above(ON and on are equivalent).TraceTimeFile ON | OFFEnables or disables trace messages that list the timing files loaded at simulationstartup. The default is OFF.October 6, 2003 Synopsys, Inc. 21

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTracePath ON | OFFEnables or disables tracing of paths to files used to determine versions of models.The default is OFF.Verbose ON | OFFEnables or disables the generation of error messages when a SmartModel instancecannot be created. The default is OFF.NoLicenseFatal ON | OFFWhen set to ON, causes the SWIFT session to send a fatal error message to thesimulator and terminate if any SmartModel in the simulation fails to authorize. Thedefault is OFF.AttentionYou must invoke the TraceTimeFile, TracePath, and NoLicenseFatalcommands before the start of the simulation run if you want them to takeeffect for that session.Fault SimulationsThe SmartModel Library fault simulation capability is folded into the logic simulationSmartModel Library so that only one set of directories and utilities need to be installedand maintained. Fault simulation availability depends on the:●●Model—Note that the following types of models are incompatible with faultsimulation:❍❍Hardware verification (HV) models are driven by PCL commands rather thanmachine instructions and do not respond adequately to propagated faults. Faultsimulation results may not be as accurate when HV models are present in thecircuit.FlexModels do not support fault simulation.Simulator—Fault analysis is supported by Mentor’s QuickFault II, VEDA’sVerdictFault, and Teradyne’s LASAR. For more information about fault simulationsupport, refer to your simulator documentation.In most cases, you can use the same circuit description for both logic and faultsimulation. However, you may need to supply different circuit stimuli for each type ofsimulation. All model messages except version, copyright, and configuration errormessages are suppressed in fault simulation. Usage and timing messages are suspendedbecause they are meaningless in a fault simulation. In order to work efficiently during afault simulation, each model manages its own diverge and converge operations.22 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsUsing FlexModels with SWIFT SimulatorsRegardless of which simulator you are using, you must configure FlexModels bydefining the required SWIFT parameters or attributes shown in Table 3 for eachFlexModel instance in your design. You configure FlexModels when you instantiatethem in your design using these SWIFT parameters. This could take the form of Verilogdefparams, VHDL generics, or symbol properties, depending on the simulator you areusing.Table 3: FlexModel SWIFT ParametersParameter a Data Type DescriptionFlexTimingModeFLEX_TIMING_MODE_OFF(default)FLEX_TIMING_MODE_ONFLEX_TIMING_MODE_CYCLEDisables/enables timing simulation.(For Verilog, prepend a back quote(‘) to the constant.)Note: C-only Command Mode userscan set this parameter to:- “0” for timing mode off- “1” for timing mode on- “2” for cycle-based timingTimingVersion Model timing version The FlexModel timing version. Referto the individual FlexModeldatasheets for available timingversions.DelayRange “MIN”, “TYP”, “MAX” (default) If you set FlexTimingMode to on,you can select MIN, TYP, or MAXdelay values with this parameter.FlexModelId “instance_name” A unique name that identifies eachFlexModel instance. This name isalso used by the flex_get_inst_handlecommand to get an integer instancehandle.Note: Used only with _fx modelsFlexModelId_cmd_stream “instance_name” A unique name that identifies eachFlexModel instance or commandstream. This name is also used by theflex_get_inst_handle command toget an integer instance handle. Forinformation on cmd_stream names,refer to the individual FlexModeldatasheets.Note: Used only with _fz models.October 6, 2003 Synopsys, Inc. 23

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTable 3: FlexModel SWIFT Parameters (Continued)Parameter a Data Type DescriptionFlexCFile “path_to_C_file -u | -c” Specifies the path to an executable Cprogram and whether to start up incoupled (-c) or uncoupled (-u) mode.Uncoupled mode is the default.Note: Used only with _fx models forC-only Command Mode.FlexModelSrc_cmd_stream “path_to_C_file -u | -c” If you want to control a FlexModelusing C-only Command Mode,change the default value forcmd_stream (HDL) to the name ofthe command stream defined in theindividual FlexModel datasheets.Use this parameter to specify the pathto an executable C program andwhether to start up in coupled (-c) oruncoupled (-u) mode. Uncoupledmode is the default.Note: Used only with _fz models forC-only Command Mode.a. Some FlexModels have additional SWIFT parameters that need to be specified to configure internalmemory (for example, the usbhost_fz). For details, refer to the individual FlexModel datasheets.24 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with Simulatorsflexm_setup Command ReferenceIn addition to specifying SWIFT parameters, you must run the flexm_setup utility eachtime you install a new or updated FlexModel into your $LMC_HOME tree. Thisensures that you pick up the latest package files for that version of the model.Syntaxflexm_setup [-help] [-dir path] modelArgumentmodelSwitches-help-d[ir] pathPathname to the FlexModel you want to set up.Prints help information.Copies the contents of the FlexModel’s versioned src/verilogand src/vhd directories into path/src/verilog and path/src/vhdl.The directory specified by path must already exist.ExamplesWhen run without the -dir switch, flexm_setup just prints the name of the versioneddirectory of the selected model’s source files# Lists name of versioned directory containing source files% flexm_setup mpc860_fxWhen run with the -dir switch pointing to your working directory, flexm_setup copiesover all the versioned package files you need to that working directory.# Creates copy in ‘flexmodel’ directory of model source files% mkdir workdir% flexm_setup -dir workdir mpc860_fxYou should not use flexm_setup to update models within an existing $LMC_HOMEtree. That is, do not use the $LMC_HOME tree as the equivalent of workdir as shown inthe previous examples. The potential exists to recursively copy a directory into itselfuntil you have no remaining disk space. $LMC_HOME should be a read-only directory,and only modified by your system administrator.October 6, 2003 Synopsys, Inc. 25

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideInstantiating FlexModels with C-only Command ModeC-only Command Mode is how you use FlexModels on SWIFT simulators withstandard FlexModel integrations. With C-only Command Mode, all model commandscome from an external compiled C program that you point to using the FlexCFileSWIFT parameter. For users familiar with Synopsys Hardware Verification models, thisis similar to setting the PCLFile parameter to point to the location of a compiled PCLprogram. In addition, you must also set the FlexModelId parameter, which does not havea default value. To generate model wrappers and instantiate models, you use the samesimulator-specific procedures as you would for traditional SmartModels. Note thatFlexModels are shipped with generated wrapper files for Verilog and VHDLtestbenches. These wrapper files are one of the file sets copied into your workingdirectory using the flexm_setup utiltiy.The individual FlexModel datasheets document the command syntax and examples forissuing model commands from Verilog, VHDL, VERA, or C. However, only simulatorswith custom integrations allow you to issue FlexModel commands from Verilog,VHDL, VERA, C, or some combination of these. SWIFT simulators with standardintegrations must stick to C-only Command Mode for issuing commands toFlexModels.To use C-only Command Mode, follow these steps:1. If you are using an HDL-based simulator, generate a model wrapper file(model_fx.v or model_fx.vhd) using your simulator vendor’s procedure. Use themodel wrapper to instantiate the model in your design. Add the FlexCFile parameter(for _fx models) or FlexModelSrc_cmd_stream parameter (for _fz models) to themodel instantiation and point it to the location of your_compiled_C_file that youcreate to drive commands into the model. Modify other SWIFT parameters in themodel wrapper as needed. Here are some examples for how to instantiate an _fxmodel for use with C-only Command Mode:VHDL:U1: pcimasterGENERIC MAP(FlexModelId => "modelId_1",FlexCFile => "./tb.o",FlexTimingMode => "1",TimingVersion => "pcimaster",DelayRange => "MAX"Verilog:defparamu1.FlexModelId = "modelId_1",u1.FlexCFile = "./tb.o",u1.FlexTimingMode = "1",26 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with Simulatorsu1.TimingVersion = "pcimaster",u1.DelayRange = "MAX";For both of these examples, the C testbench file must have the same instance name,as follows:int Id_1, status;char *sInstName = "modelId_1";/* Get the instance handle */flex_get_inst_handle(sInstName,&Id_1, &status);2. Create a working directory and run flexm_setup to make a copy of the model’s Cobject file there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 4 lists the files that flexm_setup copies to your workingdirectory.Table 4: FlexModel C-only Command Mode FilesFile Name Description Locationmodel_pkg.o Model-specific functions for UNIX. workdir/src/C/3. Compile the C object files in with the C program that you write to drive commandsinto the model (represented in the following examples as your_C_file.c). Note thatthese examples include creation of a working directory (workdir) and runningflexm_setup, as explained in the previous step. The compile line differs based onyour platform:a. for HP-UX 32-bit systems, you need to link in the -LBSD library as shown inthe following example:% mkdir workdir% flexm_setup -dir workdir model_fx% /bin/c89 -o executable_name \your_C_file.c \workdir/src/C/hp700/model_pkg.o \$LMC_HOME/lib/hp700.lib/flexmodel_pkg.o \-I$LMC_HOME/sim/C/src \-Iworkdir/src/C \-lBSDb. For Solaris 32-bit systems, you need to link in the -lsocket library as shown inthe following example:October 6, 2003 Synopsys, Inc. 27

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration Guide% mkdir workdir% flexm_setup -dir workdir model_fx% /SUNWspro5/SUNWspro/bin/c89 -o executable_name \your_C_file.c \workdir/src/C/solaris/model_pkg.o \$LMC_HOME/lib/sun4Solaris.lib/flexmodel_pkg.o \-I$LMC_HOME/sim/C/src \-Iworkdir/src/C \-lsocketc. For HP64:% mkdir workdir% flexm_setup -dir workdir model_fx% /bin/c89 -o executable_nameyour_C_file.cworkdir/src/C/hp64/model_pkg.o$LMC_HOME/lib/hp64.lib/flexmodel_pkg.o-I$LMC_HOME/sim/C/src-Iworkdir/src/C+DD64 +DA2.0W +DS2.0Wd. For Sparc64:% mkdir workdir% flexm_setup -dir workdir model_fx% /d/SUNWspro5/SUNWspro/bin/c89 -o executable_nameyour_C_file.cworkdir/src/C/sparc64/model_pkg.o$LMC_HOME/lib/sparc64.lib/flexmodel_pkg.o-I$LMC_HOME/sim/C/src-Iworkdir/src/C-Xa -xarch=v9-lsockete. For AIX:% mkdir workdir% flexm_setup -dir workdir model_fx% /bin/cc -o executable_name \your_C_file.c \workdir/src/C/ibmrs/model_pkg.o \${LMC_HOME}/lib/ibmrs.lib/flexmodel_pkg.o \-Iworkdir/src/C \-I${LMC_HOME}/sim/C/src \-ldl28 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with Simulatorsf. For Linux:% mkdir workdir% flexm_setup -dir workdir model_fx% gcc -o executable_name \your_C_file.c \workdir/src/C/x86_linux/model_pkg.o \${LMC_HOME}/lib/x86_linux.lib/flexmodel_pkg.o \-Iworkdir/src/C \-I${LMC_HOME}/sim/C/srcThe C executable file that you created in this step is the program that you point to usingthe FlexCFile SWIFT attribute for the model instance in your design.Using DesignWare Memory Models withSWIFT SimulatorsDesignWare Memory Models (DWMM) are binary simulation models. All DWMMmodels have an _mx extension in the model name: model_mx.DWMM models are available on several SWIFT simulators. This manual explains howto connect these models to the supported simulators.Regardless of the simulator you use, you must configure your DWMM models for thesimulator using the required SWIFT parameters, as explained in the next section.DesignWare Memory Model SWIFT ParametersDWMM model attributes — or parameters — are model-specific values needed by thesimulator to configure a model. You configure DWMM models when you instantiatethem in your design using these SWIFT parameters. This could take the form of Verilogdefparams or VHDL generics, or symbol properties depending on the simulator you areusing. Table 5 explains how to configure DesignWare Memory Models using therequired SWIFT parameters.Table 5: DesignWare Memory Model SWIFT ParametersParameter Usage Valid Values, Examples, &DefaultsModelIdUse this parameter to specify a uniquehandle for a model instance. You use theModelId in testbench commands to modelinstances. The ModelId is also used inmessages to indicate which model instanceis issuing the message.Valid values are positive integers inquoted strings, and “-2”.Example: “8”Default: “-2”Note: Do not use the “-2” defaultvalue.October 6, 2003 Synopsys, Inc. 29

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsModelAliasThis is the same as the ModelId, except thatyou can use a unique string that is easier foryou to remember than a ModelId integer.The ModelAlias is also handy for logicaladdress mapping. For example, if you hadfour 8-bit memory devices strung togetherin a design, you could alias their modelnames so that you can sequence testbenchcommands to the models correctly:● first_mem●●●second_memthird_memfourth_memValid values are quoted strings.Example: “first_mem”Default: None. If you don’t specifya ModelAlias, this feature isdisabled.Note: The default value in themodel wrapper file is “.”, which justmeans that this feature is off.TimingVersionUse this parameter to specify the timingversion that a model instance uses whenscheduling changes on its outputs orchecking setup and hold times on its inputs.Note: If you set this parameter to “none”,the model operates in function-only mode,with no timing.Valid values are the timing versionssupported by the model, in quotedstrings, or “none”, which specifiesfunction-only model operation.Example: “7A”Default: Timing is on. The defaultspeed-grade is model-specific—seethe model wrapper file.Note: For a list of supportedcomponents or timing versions, seethe individual model datasheets.DelayRangeUse this parameter to specify a propagationdelay range for a model instance.Valid values are “min”, “typ”, and“max.”Example: “TYP”Default: “max”Note: This setting in not casesensitive.30 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsMemoryFileMessageLevelUse this parameter to specify the file nameof a memory image file to load atsimulation startup for a model instance.Use this parameter to control the type ofmessages issued by the model instanceduring simulation.In general, the higher the decimal numberyou specify, the more messages you get.Each message type has an associateddecimal value. Add the decimal valuestogether for all the message types that youwant the model to generate, and use thatnumber to configure the MessageLevelparameter. Here are the decimal values forthe different types of messages:Message Type Decimal ValueError 1Warning 2Timing 4X-handling 8Info 16Total ............................. 31This file must be a simple text file inthe Synopsys memory image file(MIF) format or Verilog $readmemhformat. Specify the file name in aquoted string.Example: “./mem.dat”Default: None. If you don’t specifya MemoryFile, this feature isdisabled.Note: The default value in themodel wrapper file is “.”, which justmeans that this feature is off.Valid values are positive integersbetween 1 and 31 within quotedstrings that represent the decimalvalues of the bit mask for eachmessage type.Examples: For example, set thisparameter to “11” to enable Error(1), Warning (2), and X-handling(8) messages.Or, set this parameter to “5” toenable just Error (1) and Timing (4)messages.Default: “15”.The default value of “15” causes themodels to generate messages inthese categories:Error (1)Warning (2)Timing (4)X-handling (8)Info messages are disabled bydefault. To enable them, add thedecimal value 16 to your sum forthis parameter.Note: Fatal messages are alwaysenabled.October 6, 2003 Synopsys, Inc. 31

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsDefaultDataUse this parameter to specify the defaultvalues for uninitialized memory addressesfor a model instance. These are the defaultvalues that are used for the memory if youdon’t preload the model using aMemoryFile.If you don’t specify a memory width equalto the width of the model’s memory, themodel loads the right-most bits in each rowof memory with the specified values andleft fills the unspecified memory locationswith zeros.Benefit: Using the DefaultData parameterallows you to specify memory contentswithout consuming any workstationmemory during simulation.Valid values: Bit vectors in quotedcharacter strings represented asbinary (b), decimal (d), hexadecimal(h), X, or octal (o).Valid formats:– Verilog: ’[b|o|d|h]– VHDL: [b|o|x]“”The default radix for VHDL isbinary. VHDL values can includeunderscore characters to improvereadability.Examples:Note: DefaultData values must bepresented as strings (insidequotation marks).– Hexadecimal values:– “8’h5f” (Verilog)– “x\”5f\”” (VHDL —backslashes are needed toescape the double quotes)– Binary values:– “8’b01011111” (Verilog)– “01011111” (VHDL — defaultradix is binary)– “0101_1111” (VHDL)– Octal values:– “8’o137” (Verilog)– “o\”137\”” (VHDL)Default: Model-specific — seemodel wrapper file.If you omit DefaultData, the valueused will be set inside the modelwrapper file.Note: Some memory models settheir memories to all 1s or someother value. When you set theDefaultData parameter, youoverride those settings.32 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsModelConfigUse this parameter to set values in a 32-bitcontrol word that configures variousaspects of model operation, such as theoptional power-on sequence in SDRAMdevices.Valid values are 32-bit vectors inquoted strings represented as binary(b), decimal (d), hexadecimal (h), oroctal (o). Valid formats are VHDLand Verilog.Example: “32’hffffffff” (Verilog)Example: X“ffffffff” (VHDL)Default: Model-specific. See theindividual model datasheets forinformation on what each bit in thecontrol word represents in terms ofmodel operation.Instantiating DesignWare Memory ModelsFirst, generate a model wrapper file, as explained in the chapter for your simulator inthis manual. The model wrapper is a .v or .vhd file that contains most of the informationneeded to instantiate the model. You must compile this file in with your simulatorexecutable, but values you set in your model instantiation in the testbench overridecorresponding values set in the model wrapper file. In other words, the model wrapperfile and model instantiation are two different things that happen to contain overlappinginformation.Then, instantiate the model in your testbench. For example, in your model instantiationin the testbench, you must map the model’s ports to signals in your design, and modifySWIFT parameters as needed (see Table 5 for valid values and examples). Here aresome VHDL and Verilog instantiation examples for a Designware Memory Model. Notethe _mx extension that is present in the model name for all DesignWare MemoryModels.HintFor model-specific instantiation examples that include correct port namesand default values for the required SWIFT parameters, see the individualmodel datasheets.You can cut-and-paste the model instantiation right out ofthe model datasheet and drop it into your testbench. You can access thecorrect model datasheet for the version of the model that you are using withthe sl_browser tool ($LMC_HOME/bin/sl_browser).October 6, 2003 Synopsys, Inc. 33

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideVHDL Example InstantiationU0: cy62128_mxGENERIC MAP(DefaultData => "11111111",DelayRange => "Max",MemoryFile => "mem.dat",MessageLevel => "15",ModelAlias => "TB_CMD_TEST",ModelConfig => "x\0000 0000\",ModelId => "99999",TimingVersion => "55")PORT MAP(a => a,ce1_n => ce1_n,ce2 => ce2,io => io,oe_n => oe_n,we_n => we_n);NoteThe ModelConfig values in model wrappers for both VHDL and Verilog aregenerated in Verilog format by default (for example, “32’h0” in the abovemodel instantiation). You can change this value to any valid 32-bit vector ina quoted string, as explained in Table 5.Verilog Example Instantiationcy62128_mx model1(.a ( a ),.ce1_n ( ce1_n ),.ce2 ( ce2 ),.io ( io ),.oe_n ( oe_n ),.we_n ( we_n ) )defparammodel1.DefaultData = "8'b11111111",model1.DelayRange = "Max",model1.MemoryFile = "mem.dat",model1.MessageLevel = "15",model1.ModelAlias = "TB_CMD_TEST",model1.ModelConfig = "32'h0",model1.ModelId = "99999",model1.TimingVersion = "55" ;34 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsInstantiating DesignWare Memory Models in SystemCUse this general procedure to instantiate DWMM models in SystemC.1. Generate the model wrapper files as described in “Using DesignWare MemoryModels with SystemC” on page 264.The resulting model wrapper files model.h and model.cpp contain the SystemCinterface to the DWMM model.2. The model.h wrapper file defines the model’s public interface, and must be includedwithin any file in which you instantiate the model. For example:#include "model.h"3. Instantiate the model as shown in the example included in the model’s .h wrapperfile.Constructor ArgumentsEach DWMM model requires seven string arguments in the call to its constructor, asshown in the following example of a DWMM model’s constructor definition:(sc_module_name Name,const string& DefaultData,const string& MemoryFile,const string& MessageLevel,const string& ModelAlias,const string& ModelConfig,const string& ModelId);These seven arguments relate directly to the model’s SWIFT parameters, which areattributes used to configure the model.The first argument, Name, represents the parameter InstanceName as described inTable 2, “SmartModel SWIFT Parameters” on page 19.The other six arguments relate directly to the DWMM-specific parameters of the samename, as described in Table 5, “DesignWare Memory Model SWIFT Parameters” onpage 29.HintSee your model’s datasheet for configuration information. You can accessthe datasheet using the sl_browser tool ($LMC_HOME/bin/sl_browser).October 6, 2003 Synopsys, Inc. 35

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideNoteTwo DWMM parameters, DelayRange and TimingVersion, have not beenmade public in the DWMM SystemC interface. These two parameters areused to configure propagation delays within HDL simulations, and areabsent from the DWMM SystemC interface since SystemC does not supportthe use of propagation delays.Under the DWMM SystemC interface, the DelayRange attribute is ignoredand the TimingVersion attribute is hard-coded as “none” to enforce cyclebased(“function-only”) behavior.SystemC Example Instantiation// Instantiating a cy62128 DWMM modelcy62128_mx U0("U0", // InstanceName"11111111", // DefaultData"mem.dat", // MemoryFile"15", // MessageLevel"TB_CMD_TEST",// ModelAlias"32'h0", // ModelConfig"99999" // ModelId)// Binding the model's ports to design signalsU0.A( A );U0.CE1_N( CE1_N );U0.CE2( CE2 );U0.IO( IO );U0.OE_N( OE_N ),U0.WE_N( WE_N );NoteThe DWMM SystemC interface requires all model port names to beuppercase.36 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 1: Using Synopsys Models with SimulatorsUsing Hardware Models with DifferentSimulatorsAfter you install your hardware modeling system, the final task is to link your simulatorwith the Synopsys Simulator Function Interface (SFI). Procedures for linking thesimulator with the SFI are specific to the particular simulator.Linking Other Supported SimulatorsBecause many hardware modeling features are provided through the SFI software, thefunctionality of your environment is determined by the version of the SFI that isintegrated with your simulator. Some simulators can be dynamically or statically linkedon site with the most recent SFI. For the current list of simulators and versions that aresupported for dynamic or static linking on site with the SFI, refer to Hardware ModelingSupported Platforms and Simulators.If you use one of the simulators on this list, you can link your simulator with the mostrecent version of the SFI libraries on the distribution media, allowing you to takeadvantage of the latest hardware modeling system software enhancements and bugfixes. Some simulators have additional requirements. For information, refer to yoursimulator vendor’s documentation.If you use a simulator that is not on the list, consult your simulator vendor about whichversion of the SFI has been integrated with your simulator. Depending on the version ofthe SFI, you should be able to install and use the most recent Runtime ModelerSoftware, although you may not be able to take advantage of all hardware modelingsystem software enhancements and fixes.IKOS VoyagerFor information on this interface, refer to the Voyager/LM Hardware Interface chapterof the Voyager Series User’s Guide, Volume 4.Do not install the hardware modeling system software under the $VOYAGER_HOMEdirectory, or files could be overwritten and the installation corrupted. The IKOS-createdsms directory (under $VOYAGER_HOME) and the Synopsys-created sms directorymust be kept separate.Teradyne LASARYou can dynamically link the SFI with LASAR. For complete Teradyne-specificinstallation information, refer to Teradyne's LASAR Manager Guide for UNIX Systems.October 6, 2003 Synopsys, Inc. 37

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideVEDA VulcanYou can dynamically link the SFI with Vulcan at simulator runtime. For current linkinginformation, please contact VEDA technical support directly.Viewlogic Fusion ViewSimYou can statically link the SFI on-site with ViewSim. For information, refer to theViewlogic Fusion ViewSim manual or contact Viewlogic technical support directly at 1-800-223-8439. In addition, Synopsys provides a SOLV-IT! article with someinformation. For instructions on accessing SOLV-IT!, refer to “Getting Help” onpage 14.Supporting 32-bit Libraries on 64-bitPlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.38 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys Models2Using VCS with Synopsys ModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with VCS. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 40● “Using SmartModels with VCS” on page 42● “Using FlexModels with VCS” on page 44● “Using DesignWare Memory Models with VCS” on page 53● “Using Hardware Models with VCS” on page 55HintThis chapter includes a script that you can use to run any FlexModelexamples testbench with minimal setup required. You can cut and paste thescript directly from this PDF file. Refer to “Script for Running FlexModelExamples in VCS” on page 51.October 6, 2003 Synopsys, Inc. 39

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideSetting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases the procedures that follow in this chapter include steps forsetting additional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or Designware Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installation2. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list to specify thesearch path in your variable setting.CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.3. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.4. Depending on your platform, set your library search path variable to point to theplatform-specific directory in $LMC_HOME, as shown in the following examples:Solaris 32-bit:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATH40 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsAIX:% setenv LIBPATH $LMC_HOME/lib/ibmrs.lib:$LIBPATH% setenv LD_LIBRARY_PATH $LMC_HOME/lib/ibmrs.lib:$LD_LIBRARY_PATHHP-UX 32-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$SHLIB_PATHSPARC64% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sparc64.lib:$LD_LIBRARY_PATHHP64% setenv SHLIB_PATH $LMC_HOME/lib/hp64.lib:$SHLIB_PATH5. Set the VCS_HOME variable to the location of your VCS installation tree, as shownin the following example, and make sure that VCS is set up properly in yourenvironment:% setenv VCS_HOME VCS_install_path6. Set the VCS_SWIFT_NOTES variable to 1, as shown in the following example:% setenv VCS_SWIFT_NOTES 1VCS_SWIFT_NOTES enables the printf Processor Control Language (PCL)command. In addition, if this variable is not set, then no information, note, warning,or error messages from a SWIFT model will appear in the simulation transcriptwindow.Supporting 32-Bit Libraries on 64-Bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.October 6, 2003 Synopsys, Inc. 41

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideUsing SmartModels with VCSTo use SmartModels with VCS, follow this procedure:1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. Synopsys provides a tool, vcs_sg, that allows you to generate multiple modelwrapper files. You must select VCS as your Verilog simulator during theSmartModel installation in order to have vcs_sg available. It will be installed as$LMC_HOME/bin/vcs_sgThe vcs_sg tool also extends the usefulness of the model wrapper files generated byVCS in two ways:❍it adds statements that allow the DelayRange to be controlled by the VCScommand line +define parameters (or a defparam in your testbench)❍ it adds a check for the VCS command line +define+SwiftChecksOff parameterthat turns constraints off.You can change the default name of the generated wrapper files (model.swift.v), aswell as the location that the generated wrappers are written to. Use the followingcommand to return the usage message for the vcs_sg tool.% $LMC_HOME/bin/vcs_sg -h3. Instantiate SmartModels in your design, defining the ports and defparams asrequired. For details on the required SWIFT parameters and SmartModelinstantiation examples, refer to “SmartModel SWIFT Parameters” on page 19.4. Invoke the VCS simulator as shown in the following examples:Solaris (32-bit):% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-l vcs_sim.log \-Mupdate \-RIHP-UX (32-bit):% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-l vcs_sim.log \-Mupdate \-RI42 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsSparc64:% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-full64 \-l vcs_sim.log \-Mupdate \-RIHP64:AIX:% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-full64 \-l vcs_sim.log \-Mupdate \-RI% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-l vcs_sim.log \-Mupdate \-RI \-LDFLAGS -lldLinux:% $VCS_HOME/bin/vcs -lmc-swift model.swift.v model_tb.v \-l vcs_sim.log \-Mupdate \-RI \-LDFLAGS -rdynamicwhere model.swift.v is the template you created in the previous step and model_tb.vis the testbench where the model is instantiated. Each model instantiated in thetestbench must have a model.swift.v wrapper file listed on the VCS invocation line.VCS SmartModel ExplanationTable 6 lists each line in the invocation examples above, along with explanations forwhat each one does.Table 6: VCS SmartModel ExplanationLine ReferenceDescription$VCS_HOME/bin/vcs-lmc-swift model.swift.v model_tb.vPath to the file that starts the VCS simulator, aswitch that causes VCS to load the SWIFTinterface, and then the specified model wrapper andVerilog testbench files.October 6, 2003 Synopsys, Inc. 43

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideTable 6: VCS SmartModel Explanation (Continued)Line ReferenceDescription-l vcs_sim.log Specifies a log file where VCS writes compilationand simulation messages.-Mupdate-RI-LDFLAGS switchesThis specifies incremental compilation, whichcauses VCS to compile only the modules that havechanged since the last run.This makes VCS run interactively. VCS invokes theVirSim GUI after compilation and pauses thesimulator at time zero.Additional platform-specific switches that may beneeded.-full64 Compiles the design in 64 bit mode and creates a 64bit executable for simulating in 64 bit mode.Using FlexModels with VCSTo use FlexModels with VCS, follow this procedure. VCS links the external PLIroutines that contain the custom FlexModel integration code during compilation of yourdesign.1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 7 lists the files that flexm_setup copies to your workingdirectory.Table 7: FlexModel VCS Verilog FilesFile Name Description Locationmodel_pkg.incmodel_user_pkg.incVerilog task definitions for FlexModelinterface commands. This file alsoreferences the flexmodel_pkg.inc andmodel_user_pkg.inc files.Clock frequency setup and usercustomizations.workdir/src/verilog/workdir/src/verilog/44 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsTable 7: FlexModel VCS Verilog Files (Continued)File Name Description Locationmodel_fx_vcs.vmodel.vmodel_tst.vA SWIFT wrapper that you can use toinstantiate the model.A bus-level wrapper around the SWIFTmodel. This allows you to use vectoredports for the model in your testbench.A testbench that instantiates the model andshows how to use basic model commands.workdir/examples/verilog/workdir/examples/verilog/workdir/examples/verilog/3. Update the clock frequency supplied in the model_user_pkg.inc file to correspondto the CLK period you want for the model. This file is located in:workdir/src/verilog/model_user_pkg.incwhere workdir is your working directory.4. Add the following line to your Verilog testbench to include FlexModel testbenchinterface commands in your design:`include "model_pkg.inc"NoteBe sure to add model_pkg.inc within the module from which you will beissuing FlexModel commands.Because the model_pkg.inc file includes references to flexmodel_pkg.inc andmodel_user_pkg.inc, you don’t need to add flexmodel_pkg.inc ormodel_user_pkg.inc to your testbench.5. Instantiate FlexModels in your design, defining the ports and defparams as required(refer to the example testbench supplied with the model). You use the supplied buslevelwrapper (model.v) in the top-level of your design to instantiate the suppliedbit-blasted wrapper (model_fx_vcs.v).Example using bus-level wrapper (model.v) without timing:model U1 ( model ports )defparamU1.FlexModelId = “TMS_INST1”;October 6, 2003 Synopsys, Inc. 45

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideExample using bus-level wrapper (model.v) with timing:model U1 ( model ports )defparamU1.FlexTimingMode = `FLEX_TIMING_MODE_ON,U1.TimingVersion = “timingversion”,U1.DelayRange = “range”,U1.FlexModelId = “TMS_INST1”;6. Invoke VCS to compile and simulate your design as shown in the followingexamples:Solaris 32-bit:% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-lmc-swift \- RI \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog% simvHP-UX 32-bit:% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/hp700.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-lmc-swift \-RI+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \% simvSparc64:% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/sparc64.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-full64 \-lmc-swift \-RI \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog% simv46 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsHP64:AIX:% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/hp64.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-full64 \-lmc-swift \-RI+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \% simv% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/ibmrs.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-lmc-swift \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \-RI \-LDFLAGS -lld% simvLinux:% vcs workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_vcs.v \$LMC_HOME/lib/x86_linux.lib/slm_pli.o \testbench.v \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-lmc-swift \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \-LDFLAGS -rdynamic \-RI \% simvOctober 6, 2003 Synopsys, Inc. 47

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideVCS FlexModel ExamplesFirst we present a basic one-model example and then show you how to use more thanone FlexModel in the same simulation in the following sections:● “One FlexModel on Solaris (32-bit)” on page 48● “Two FlexModels on Solaris (32-bit)” on page 50● “Three FlexModels on HP-UX (32-bit)” on page 50NoteAll examples are for 32-bit versions of the models.One FlexModel on Solaris (32-bit)To use one FlexModel with VCS on Solaris, invoke the simulator as shown in thefollowing example:% $VCS_HOME/bin/vcs \`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model_tst.v \`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model.v \`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model_fx_vcs.v \+incdir+$LMC_HOME/sim/pli/src \+incdir+`$LMC_HOME/bin/flexm_setup model_fx`/src/verilog \-P $LMC_HOME/sim/pli/src/slm_pli.tab \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \+incdir+$LMC_HOME/sim/pli/src \-l vcs_sim.log \-Mupdate \-RI \-lmc-swiftwhere model is the name of the FlexModel you are using.48 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsTable 8 lists each line in the invocation example above, along with explanations forwhat each one does.Table 8: VCS With One FlexModel On 32-bit Solaris Model Explanation$VCS_HOME/bin/vcsLine Reference`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model_tst.v`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model.v`$LMC_HOME/bin/flexm_setup model_fx`/examples/verilog/model_fx_vcs.v+incdir+$LMC_HOME/sim/pli/src+incdir+`$LMC_HOME/bin/flexm_setupmodel_fx`/src/verilogDescriptionPath to the file that starts the VCS simulator.Specifies the path to the model testbench file.Specifies the path to the model Verilogwrapper file.Specifies the path to the model VCS templatefile.Includes the path to the flexmodel_pkg.incfile, which contains Verilog task definitionsfor general FlexModel interface commands.Includes the path to the model-specificVerilog task files, including model_pkg.inc.-P $LMC_HOME/sim/pli/src/slm_pli.tab Specifies the FlexModel/MemPro PLI tableentry file.$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o Specifies the platform-specific PLI objectfile.-l vcs_sim.log Specifies a log file where VCS writescompilation and simulation messages.-Mupdate-RI-lmc-swift-full64This specifies incremental compilation,which causes VCS to compile only themodules that have changed since the last run.This makes VCS run interactively. VCSinvokes the XVCS GUI after compilation andpauses the simulator at time zero.This switch causes VCS to load the SWIFTinterface.This is not shown in the examples, but mustbe used if you are simulating in 64-bits.Compiles the design in 64 bit mode andcreates a 64 bit executable for simulating in64 bit mode.October 6, 2003 Synopsys, Inc. 49

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideTwo FlexModels on Solaris (32-bit)This example shows how to use the mpc740_fx and mpc750_l2_fx FlexModels togetherwith VCS on Solaris. Invoke the simulator as shown in the following example:% $VCS_HOME/bin/vcs \`$LMC_HOME/bin/flexm_setup mpc750_l2_fx`/examples/verilog/mpc750_l2_tst.v \`$LMC_HOME/bin/flexm_setup mpc750_l2_fx`/examples/verilog/mpc750_l2.v \`$LMC_HOME/bin/flexm_setup mpc750_l2_fx`/examples/verilog/mpc750_l2_fx_vcs.v \`$LMC_HOME/bin/flexm_setup mpc740_fx`/examples/verilog/mpc740.v \`$LMC_HOME/bin/flexm_setup mpc740_fx`/examples/verilog/mpc740_fx_vcs.v \+incdir+$LMC_HOME/sim/pli/src \+incdir+`$LMC_HOME/bin/flexm_setup mpc750_l2_fx`/src/verilog \+incdir+`$LMC_HOME/bin/flexm_setup mpc740_fx`/src/verilog \-P $LMC_HOME/sim/pli/src/slm_pli.tab \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \+incdir+$LMC_HOME/sim/pli/src \-l vcs_sim.log \-Mupdate \-RI \-lmc-swiftThree FlexModels on HP-UX (32-bit)This example shows how to use the PCI system testbench and the PCI FlexModelstogether with VCS on HP-UX. Follow these steps:1. Set up the PCI system testbench as shown in the following example:% mkdir pci_tb% $LMC_HOME/bin/flexm_setup pcimaster_fx -dir pci_tb% $LMC_HOME/bin/flexm_setup pcimonitor_fx -dir pci_tb% $LMC_HOME/bin/flexm_setup pcislave_fx -dir pci_tb50 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys Models2. Invoke the VCS simulator as shown in the following example:% $VCS_HOME/bin/vcs \./pci_tb/examples/verilog/pcisys_tst.v \./pci_tb/examples/verilog/pcimaster.v \./pci_tb/examples/verilog/pcimaster_fx_vcs.v \./pci_tb/examples/verilog/pcislave.v \./pci_tb/examples/verilog/pcislave_fx_vcs.v \./pci_tb/examples/verilog/pcimonitor.v \./pci_tb/examples/verilog/pcimonitor_fx_vcs.v \+incdir+./pci_tb/src/verilog \+incdir+$LMC_HOME/sim/pli/src \$LMC_HOME/lib/hp700.lib/slm_pli.o \-P $LMC_HOME/sim/pli/src/slm_pli.tab \-l vcs_sim.log \-Mupdate \-RI \-lmc-swiftScript for Running FlexModel Examples in VCSOn page 52 is a Perl script (Figure 1) that you can use to run VCS on a FlexModelexample testbench. You can use this script on any installed FlexModel because each onecomes with a prebuilt testbench example that shows how to use the model commandsand all the Verilog wrapper and task definition files that you need. This script runs onHP-UX and Solaris.To invoke VCS on a FlexModel and its example testbench, follow these steps:1. Use the Acrobat Reader’s text selection tool to select the script shown in Figure 1and copy the contents to a local file named run_flex_examples_in_vcs.pl.2. Save the file and change the permissions so that the file is executable (chmod 775).3. Invoke the script as shown in the following examples:% run_flex_examples_in_vcs.pl model_fxwhere model_fx is the name of the FlexModel you want to run.October 6, 2003 Synopsys, Inc. 51

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideNoteThis script was developed for internal use and is made available for userconvenience. It is not actively maintained as part of the licensed software.#!/usr/local/bin/perl# $Revision$$output_file = "Example_Simulator_Run_Script";die "\nERROR running $0: ", "No FlexModel name given\n\n", unless($ARGV[0] );$LmcHome = $ENV{ LMC_HOME }; die "ERROR running $0: ", "The LMC_HOME environmentvariable must be set.\n" unless( $LmcHome );$VcsHome = $ENV{ VCS_HOME };die "ERROR running $0: ", "The VCS_HOME environment variable must be set.\n" unless($VcsHome );$VcsSwiftNotes = $ENV{ VCS_SWIFT_NOTES };die "ERROR running $0: ", "The VCS_SWIFT_NOTES environment variable must be set.\n","\nSet VCS_SWIFT_NOTES to the value 1\n\n", unless( $VcsSwiftNotes );require "$LmcHome/lib/bin/libmdl01003.pl";$Platform = GetPlatform();$Platform_lib = PlatformToLibDir($Platform);#%platform_suffix = ( hp700 => "o", solaris => "o");$suffix = $platform_suffix{ $Platform };$flexmodel_name = $ARGV[0];$model_path = $LmcHome . "/models/" . $flexmodel_name;if ( -e $model_path ) {}else { die "\nERROR running $0: ", "FlexModel $flexmodel_name Does not Exist inLibrary\n\n"; }$version_path = `$LmcHome/bin/flexm_setup $flexmodel_name`;chomp($version_path);if ( $flexmodel_name =~ /_fx/ ) { $flexmodel_name =~ s/_fx//g; $flex_or_c = "_fx";}elsif ($flexmodel_name =~ /_fz/ ) {$flexmodel_name =~ s/_fz//g;$flex_or_c = "_fz";}else { die "\nERROR running $0: ", "$flexmodel_name is not a FlexModel. Model musthave an _fx or _fz to be a FlexModel\n\n";}$execute_command = $VcsHome . "/bin/vcs -Mupdate -RI -l vcs_sim.log ". $version_path . "/examples/verilog/". $flexmodel_name . "_tst.v +incdir+". $version_path . "/src/verilog +libext+.inc ". $version_path . "/examples/verilog/" . $flexmodel_name . ".v ". $version_path . "/examples/verilog/". $flexmodel_name . $flex_or_c . "_vcs.v ";if ( $Platform eq "pcnt" ) {$execute_command = $execute_command . $LmcHome . $Platform_lib . "slm_pli_vcs." .$suffix;}else {$execute_command = $execute_command . $LmcHome . $Platform_lib . "slm_pli.o" .$suffix;}$execute_command = $execute_command . " -P " . $LmcHome . "/sim/pli/src/slm_pli.tab". " -lmc-swift +incdir+" . $LmcHome . "/sim/pli/src"; print "$execute_command\n";open(OFILE,"> $output_file") || die " Could not create file : $output_file\n";print OFILE ("# This is an example of VCS command line to run the\n");print OFILE ("# supplied FlexModel testbench.\n");print OFILE ("# Note: The model version was calculated using the flexm_setupcommand\n");print OFILE ("\n$execute_command\n");close(OFILE); system($execute_command);Figure 1: run_flex_examples_in_vcs.pl Script52 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsExample Simulator Run ScriptThe run_flex_examples_in_vcs.pl script also creates an example simulator run script inyour current working directory for the specified model. You can use this run script toinvoke VCS after running the run_flex_examples_in_vcs.pl script. The followingexample shows the contents of the “Example_Simulator_Run_Script” after running therun_flex_examples_in_vcs.pl script using the mpc860_fx model.# This is an example of VCS command line to run the supplied FlexModeltestbench.# Note: The model version was calculated using the flexm_setup command/d/vcs501/vcs5.0.1A/bin/vcs -Mupdate -RI -l vcs_sim.log/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860_tst.v+incdir+/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/src/verilog +libext+.inc/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860.v/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860_fx_vcs.v /d/lmgqa2/install/lmc_home/lib/hp700.lib/slm_pli.o -P/d/lmgqa2/install/lmc_home/sim/pli/src/slm_pli.tab -lmc-swift+incdir+/d/lmgqa2/install/lmc_home/sim/pli/srcUsing DesignWare Memory Models with VCSDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have the extension “_mx” (for example, model_mx.) To use DWMMmodels with VCS, follow these steps:1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.3. Generate Verilog wrapper files for the model, as shown in the following example:% $LMC_HOME/bin/vcs_sg -t -lc -m model_mxOctober 6, 2003 Synopsys, Inc. 53

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideThis step produces a bit-blasted Verilog wrapper file named model_mx.v and abused Verilog wrapper file named model_mx_bus.v. The wrapper files both containan InstanceName parameter along with the following instructions:// Please insert instance name here...// **and uncomment this lineDo not follow these instructions. The InstanceName parameter is not needed forinstantiating DWMM models (see the next step).4. Instantiate the model_mx_bus model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).5. Invoke VCS to compile your design, as shown in the following example:% vcs \model_mx_bus.v \testbench.v \-lmc-swift \-P $LMC_HOME/sim/pli/src/slm_pli.tab \$LMC_HOME/lib/platform.lib/slm_pli.o \+incdir+$LMC_HOME/sim/pli/src54 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys ModelsNoteSolaris users: If you plan to use MemScope’s Dynamic Data Exchange(DDX) feature, include this line when you compile your design:-Xstrict=0x01 -syslib "-lpthread"These switches enable multithread processes, which is necessary for DDX tofunction. If SWIFT models from a vendor other than Synopsys are includedin the same simulation, they must also have been compiled to acceptmultithread processes. Customers should contact their vendor if they are notsure about how their non-Synopsys models support multithread processes.Other platforms: Refer to SolvNet Article 006845 on how to use the-Xstrict switch on non-Solaris platforms.6. Invoke VCS and simulate your design:% simvUsing Hardware Models with VCSTo use hardware models with VCS, follow this procedure:1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. Add the hardware model install tree to your path variable, as shown in the followingexample:% set path=(/install/sms/bin/platform/ $path)3. Set the VCS_LMC environment variable to the hm directory in the VCS install, asshown in the following example:% setenv VCS_LMC $VCS_HOME/platform/lmc/hm4. Set the LM_SFI environment variable to the SFI directory in the hardwaremodeling tree, as shown in the following example:% setenv LM_SFI hardware_modeler_install_path/sms/lib/platform/5. Set the VCS_LMC_HM_ARCH environment variable so that you can later use the-lmc-hm switch. This variable must be set to find the SFI directory in the sms/libtree, as shown in the following examples:Solaris% setenv VCS_LMC_HM_ARCH sun4.solarisOctober 6, 2003 Synopsys, Inc. 55

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideHP-UX% setenv VCS_LMC_HM_ARCH pa_hp1026. Create a Verilog HDL template for the hardware model using the lmvc_templatescript provided by VCS, as shown in the following example:% lmvc_template model_filewhere model_file is the name of the hardware model's .MDL file.For example, if your model is the TILS299, enter:% lmvc_template TILS299.MDLThis step produces a TILS299.lmvc.v file that contains the module definition withall the calls, declarations, and assignments necessary to make the file a valid VCSmodule.NoteThe lmvc_template program looks for Shell Software files in the directoriesindicated by the LM_LIB environment variable. You can modify the port listgenerated by the lmvc_template to match the existing model instantiationsby editing the .NAM file.7. Compile your description. Make sure to include the hardware model template andsupporting PLI and library files. To interface the hardware modeler to VCS, add the-lmc-hm switch to the VCS command line, as shown in the following example:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -lmc-hm -o simv \+override_model_delays +maxdelays -l vcs.log &You can optionally invoke VCS without the -lmc-hm switch by using the -P switchto point to the $VCS_LMC/lmvc.tab file and including the $VCS_LMC/lmvc.oobject file and $LM_SFI/lm_sfi.a library, as shown in the following example:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -P $VCS_LMC/lmvc.tab \$VCS_LMC/lmvc.o $LM_SFI/lm_sfi.a -o simv \+override_model_delays +maxdelays -l vcs.log &where:• vcs is the compiler• test.v is the file that is part of the top level system source files• TILS299.lmvc.v is the vcs template for the HW model• lmvc.tab is the VCS file for lmvc calls for vector logging, and timingmeasurement• lmvc.o is the object code for LMC C file (lmvc.c), which contains thedefinitions for all the lmvc tasks/functions.56 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 2: Using VCS with Synopsys Models• lm_sfi.a is the simulator function interface software that links the VCSsimulator to the hardware modeler.• +override_model_delays is a switch that allows you to specify timing otherthan typical.Notethe -RI option is not required to generate the simv file. It is used to have thesimulator automatically execute after compilation.For more information on using the .tab/.c files and options with VCS, refer to the VCSUsers's Guide.Note that in the previous VCS releases, the hardware model could only be simulatedwith typical delays. The VCS 5.2 release has removed this restriction, so you can noweither use a runtime option on the command line or make the change in the DelayRangeparameter. Note that the runtime option does override any DelayRange parameterspecification. The following excerpt is from the VCS 5.2 Release Notes:“VCS 5.2 has a new runtime option, +override_model_delays that enables you touse the +mindelays, +typdelays, or +maxdelays runtime option to specify timing inSWIFT SmartModels or Synopsys hardware models and in so doing override theDelayRange parameter in the template files for these models that otherwisespecifies the timing for the model.”Example Using Runtime OptionHere is an example using the runtime option:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -P $VCS_LMC/lmvc.tab \$VCS_LMC/lmvc.o $LM_SFI/lm_sfi.a +override_model_delays \+maxdelays -l vcs.log &Example Using DelayRange ParameterHere is an example using the DelayRange parameter:TILS299 hwm_1 ( .\SL (shift_left), .\CLK (clock),.\SR (shift_right), .\NCLR (clear),.\-G2 (g2), .\-G1 (g1), .\S1 (select_1), .\S0 (select_0),.\D/QD (bit_4), .\F/QF (bit_6), .\B/QB (bit_2),.\C/QC (bit_3), .\A/QA (bit_1), .\G/QG (bit_7), .\E/QE (bit_5),.\H/QH (bit_8), .\QA (high_bit), .\QH (low_bit) );`ifdef MAXdefparam hwm_1.DelayRange = "MAX" ;`endifOctober 6, 2003 Synopsys, Inc. 57

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideRun your simulation as usual. After running the vcs compiler, you should see acompiled simv file. To run your simulation, type in simv.You need an additional passcode to use the hardware model interface. If you do not havea passcode, contact VCS Simulation Support at 800-837-4564.VCS UtilitiesIf you want to turn on test vector logging or timing measurement, you can invoke tasks'lm_log', 'lm_log_off', 'lm_measure_time', or 'lm_measure_time_off'.instance_name.lm_measure_time;instance_name.lm_measure_time_off;where instance_name is a string that is the hierarchical path name of the instance for thehardware model. For example, assuming that our instance is top.hwm_1 with thesefeatures, it would look like the following example:module top;TILS299 hwm_1();initial begintop.hwm_1.lm_measure_time;top.hwm_1.lm_log ("file_name");#7000;endtop.hwm_1.lm_measure_time_off;top.hwm_1.lm_log_off;58 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys Models3Using ModelSim Verilog withSynopsys ModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with MTI Verilog (ModelSim/VLOG.). The proceduresare organized into the following major sections:● “Setting Environment Variables” on page 59● “Using SmartModels with ModelSim Verilog” on page 61● “Using FlexModels with ModelSim Verilog” on page 63● “Using DesignWare Memory Models with ModelSim Verilog” on page 66● “Using Hardware Models with ModelSim Verilog” on page 68Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases the procedures that follow in this chapter include steps forsetting additional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installation2. Make sure ModelSim Verilog is set up properly in your environment.October 6, 2003 Synopsys, Inc. 59

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration Guide3. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list (UNIX) orsemicolon-separated list to specify the search path in your variable setting.CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.4. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.5. Depending on your platform, set your load library variable to point to the platformspecificdirectory in $LMC_HOME, as shown in the following examples:Solaris 32-bit:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATHFor Sparc64:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sparc64.lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATHAIX:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/ibmrs.lib:$LD_LIBRARY_PATHHP-UX 32-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$SHLIB_PATHHP-UX 64-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp64.lib:$SHLIB_PATH60 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys ModelsRunning 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.Using SmartModels with ModelSim VerilogSmartModels work with ModelSim Verilog using a PLI application called LMTV that isdelivered in the form of a swiftpli_mti shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use SmartModels with the prebuilt swiftpli_mti, follow this procedure:1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Instantiate SmartModels in your design, defining the ports and defparams asrequired. For details on the required SWIFT parameters and SmartModelinstantiation examples, refer to “Using SmartModels with SWIFT Simulators” onpage 18.3. Map your work library as shown in the following example:% vlib work% vmap work workThis step produces a modelsim.ini file.4. Edit the modelsim.ini file to uncomment the Resolution statement, and set theresolution value to 100ps, as shown in the following example.Resolution = 100psOctober 6, 2003 Synopsys, Inc. 61

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideThen uncomment the libsm and libswift lines corresponding to the platform you areusing:; ModelSim’s interface to Logic Modeling’s SmartModel SWIFT software;libsm = $MODEL_TECH/libsm.sl; libsm = $MODEL_TECH/libsm.dll; Logic Modeling’s SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling’s SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling’s SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling’s SmartModel SWIFT software (Sun4 SunOS); do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib; and run "vsim.swift".; ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll; Logic Modeling's SmartModel SWIFT software (HP64); libswift = $LMC_HOME/lib/hp64.lib/libswift.sl; Logic Modeling's SmartModel SWIFT software (Sparc64); libswift = $LMC_HOME/lib/sparc64.lib/libswift.soNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using ModelSim VHDL with Synopsys Models” onpage 73).5. Compile your code as shown in the following examples:UNIX% vlog testbench model.v +incdir+$LMC_HOME/sim/pli/src6. Invoke the simulator as shown in the following examples:HP-UX 32-bit% vsim -pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl designSolaris 32-bit% vsim -pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so designHP64% vsim -pli $LMC_HOME/lib/hp64.lib/swiftpli_mti.sl designSparc64% vsim -pli $LMC_HOME/lib/sparc64.lib/swiftpli_mti.so designAIX% vsim -pli $LMC_HOME/lib/ibmrs.lib/swiftpli_mti.so design62 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys ModelsLinux% vsim -pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so designNoteFor information on LMTV commands that you can use with SmartModelson ModelSim Verilog, refer to “LMTV Commands” on page 271.Using FlexModels with ModelSim VerilogFlexModels work with ModelSim-Verilog using a PLI application called LMTV that isdelivered in the form of a swiftpli_mti shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:1. Make sure ModelSim Verilog is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in the following example:% vlib work% vmap work workThis step produces a modelsim.ini file.3. Edit the modelsim.ini file to uncomment the Resolution statement, and set theresolution value to 100ps, as shown in the following example.Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using ModelSim VHDL with Synopsys Models” onpage 73).4. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 9 lists the files that flexm_setup copies to your workingdirectory.October 6, 2003 Synopsys, Inc. 63

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideTable 9: FlexModel ModelSim Verilog FileFile Name Description Locationmodel_pkg.incVerilog task definitions for FlexModel interfacecommands. This file also references theflexmodel_pkg.inc and model_user_pkg.inc files.workdir/src/verilog/model_user_pkg.inc Clock frequency setup and user customizations. workdir/src/verilog/model_fx_mti.vmodel.vmodel_tst.vA SWIFT wrapper that you can use to instantiatethe model.A bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench.A testbench that instantiates the model and showshow to use basic model commands.workdir/examples/verilog/workdir/examples/verilog/workdir/examples/verilog/5. Update the clock frequency supplied in the model_user_pkg.inc file to correspondto the CLK period you want for the model. This file is located in:workdir/src/verilog/model_user_pkg.incwhere workdir is your working directory.6. Add the following line to your Verilog testbench to include FlexModel testbenchinterface commands in your design:`include "model_pkg.inc"NoteBe sure to add model_pkg.inc within the module from which you will beissuing FlexModel commands.Because the model_pkg.inc file includes references to flexmodel_pkg.inc andmodel_user_pkg.inc, you don’t need to add flexmodel_pkg.inc ormodel_user_pkg.inc to your testbench.7. Instantiate FlexModels in your design, defining the ports and defparams as required(refer to the example testbench supplied with the model). You use the supplied buslevelwrapper (model.v) in the top-level of your design to instantiate the suppliedbit-blasted wrapper (model_fx_mti.v).Example using bus-level wrapper (model.v) without timing:model U1 ( model ports )defparamU1.FlexModelId = “TMS_INST1”;64 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys ModelsExample using bus-level wrapper (model.v) with timing:model U1 ( model ports )defparamU1.FlexTimingMode = `FLEX_TIMING_MODE_ON,U1.TimingVersion = “timingversion“,U1.DelayRange = “range“,U1.FlexModelId = “TMS_INST1”;8. Compile your code as shown in the following examples:UNIX% vlog testbench \workdir/examples/verilog/model.v \workdir/examples/verilog/model_fx_mti.v \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog9. Invoke the simulator as shown in the following examples:HP-UX 32-bit% vsim -pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl designAIX% vsim -pli $LMC_HOME/lib/ibmrs.lib/swiftpli_mti.so designSolaris 32-bit% vsim -pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so designHP-UX 64-bit% vsim -pli $LMC_HOME/lib/hp64.lib/swiftpli_mti.sl designSPARC64% vsim -pli $LMC_HOME/lib/sparc64.lib/swiftpli_mti.so designLinux% vsim -pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so designNoteFor information on LMTV commands that you can use with FlexModels onModelSim-Verilog, refer to “LMTV Commands” on page 271.October 6, 2003 Synopsys, Inc. 65

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideUsing DesignWare Memory Models withModelSim VerilogDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx). DWMM models workwith MTI Verilog (ModelSim) using a PLI application called LMTV that is delivered inthe form of a swiftpli_mti shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:To use DWMM models with ModelSim-Verilog, follow these steps:1. Make sure ModelSim Verilog is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in this example:% vlib work% vmap work workThis produces a modelsim.ini file.3. Edit the modelsim.ini file to uncomment the Resolution statement, and set theresolution value to 100ps, as shown in the following example.Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using ModelSim VHDL with Synopsys Models” onpage 73).4. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.66 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys Models5. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.6. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxThis step produces a bused Verilog wrapper file named model_mx_bw.v.7. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).8. Compile your design as shown in the following example:% vlog testbench.v model_mx.v model_mx_bw.v \+incdir+$LMC_HOME/sim/pli/src9. Invoke the simulator as shown in the following examples:HP-UX% vsim -pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl designSolaris% vsim -pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so designLinux% vsim -pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so designOctober 6, 2003 Synopsys, Inc. 67

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideUsing Hardware Models with ModelSimVerilogTo use hardware models with ModelSim Verilog, follow this procedure. Note thathardware models are supported on ModelSim Verilog v5.4c and up.1. Make sure ModelSim Verilog is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 59.2. Open the modelsim.ini file in a text editor, and uncomment the line for Resolution,as shown in the following example:Resolution = 100ps3. ModelSim Verilog only supports dynamic linking of PLI libraries. The three waysto specify the required ModelAccess shared library, and the order in which thesimulator looks for PLI libraries, is listed below. Choose one of the followingmethods:a. Add the platform-specific shared library to the Veriuser entry in themodelsim.ini file:SolarisAIXVeriuser = mav.soVeriuser = mav.soHP-UXVeriuser = mav.slb. Add an item in the PLIOBJS environment variable list:% setenv PLIOBJS “mav.ext”c. Use the -pli switch on the simulator invocation line:% vsim -pli mav.extNoteFor steps b and c, fill in the correct extension for your platform.4. Regardless of the option you choose, you must locate the ModelAccess PLI libraryfor the simulator using a platform-specific environment variable or by specifyingthe full path to the library in Step 3. Here are examples for setting the environmentvariables which show the full paths to the libraries:68 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys ModelsSolaris% setenv LD_LIBRARY_PATH \hardware_model_install_path/sms/ma_verilog/lib/sun4_5.6/mav.soHP-UXAIX% setenv SHLIB_PATH \hardware_model_install_path/sms/ma_verilog/lib/pa_hp102/mav.sl% setenv LIBPATH \hardware_model_install_path/sms/ma_verilog/lib/rs6000_4.1.5/mav.so5. Generate a Verilog module definition or shell for each hardware model that youwant to use by running the Synopsys-provided lmvsg script, as shown in thefollowing example:% lmvsg destination_model.MDLFor this to work, the hardware_model_install_path/sms//ma_verilog/bin/platformdirectory must be in your PATH. .6. Use the Verilog module definitions to instantiate the hardware models in yourtestbench. The following example shows an example instantiation for the TILS299hardware model Notice the two “defparam” statements; the definitions of theTimingVersion (TILS299A.MDL) and DelayRange (MIN) parameters in theinstantiation override the default definitions in the model.v file (TILS299.MDL andMAX, respectively). In this example, TILS299A.MDL represents a custom timingversion that the designer wants to use instead of the default timing versionTILS299.MDL./ Instantiate UUT : ModelSource TILS299 hardware model : U1defparam U1.TimingVersion=”TILS299A.MDL”;defparam U1.DelayRange = “MIN”;TILS299 U1(.CLK (clkw),.CLR (clrw),.A (io1w[0]),.B (io1w[1]),.C (io1w[2]),.D (io1w[3]),.E (io1w[4]),.F (io1w[5]),.G (io1w[6]),.H (io1w[7]),.G1 (g1w),.G2 (g2w),.QA (qa1w),.QH (qh1w),.S0 (s0w),.S1 (s1w),October 6, 2003 Synopsys, Inc. 69

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration Guide.SL (slw),.SR (srw));7. Invoke the ModelSim Verilog simulator as shown in the following example, whichillustrates the use of the -pli switch to specify the PLI library.% vsim -pli mav_libraryModelSim Verilog UtilitiesThe following hardware model utilities are supported in ModelSim Verilog:$lm_log_test_vectors (“instance_path”, on_off, “filename”)The $lm_log_test_vectors command enables test vector logging for a specified instance,and specifies a file name for the test vector log. For a detailed syntax description, referto “$lm_log_test_vectors Command Reference” on page 99.$lm_loop_instance (“instance_path”)The $lm_loop_instance command enables the loop mode for a specified model instance.For a detailed syntax description, refer to “$lm_loop_instance Command Reference” onpage 100.$lm_timing_information (“instance_path”, “timing_option”)The $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance. For a detailedsyntax description, refer to “$lm_timing_information Command Reference” onpage 101.$lm_timing_measurements (“instance_path”, on_off, “filename”)The $lm_timing_measurements command enables timing measurements for a specifiedmodel instance. It is not supported for ModelSource 3200 and 3400. For a detailedsyntax description, refer to “$lm_timing_measurements Command Reference” onpage 102.70 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys Models$lm_unknowns (“option=value” [,”option=value”,...] [, “device_or_pin”])The $lm_unknowns command lets you override the hardware modeler’s defaulthandling of unknown values for specified instances or pins, or for all hardware modelinstances in the simulation. For a detailed syntax description, refer to “$lm_unknownsCommand Reference” on page 103.October 6, 2003 Synopsys, Inc. 71

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration Guide72 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Models4Using ModelSim VHDL with SynopsysModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with ModelSim VHDL. The procedures are organizedinto the following major sections:● “Setting Environment Variables” on page 73● “Using SmartModels with ModelSim VHDL” on page 75● “Using FlexModels with ModelSim VHDL” on page 79● “Using DesignWare Memory Models with ModelSim VHDL” on page 82● “Using Hardware Models with ModelSim VHDL” on page 84Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model typesspecified, skip that step. In some cases, the procedures that follow in this chapter includesteps for setting additional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installationOctober 6, 2003 Synopsys, Inc. 73

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration Guide2. Make sure that ModelSim VHDL is set up properly in your environment, and set anMTI_HOME variable to point to the location of your ModelSim VHDL installationtree, as follows:% setenv MTI_HOME path_to_MTI-VHDL_installation3. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list (UNIX) orsemicolon-separated list to specify the search path in your variable setting.CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.4. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.5. Depending on your platform, set your load library variable to point to the platformspecificdirectory in $LMC_HOME, as shown in the following examples:Solaris 32-bit:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATHFor Sparc64:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sparc64.lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATHAIX:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/ibmrs.lib:$LD_LIBRARY_PATH74 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys ModelsHP-UX 32-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$SHLIB_PATHHP-UX 64-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp64.lib:$SHLIB_PATHRunning 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.Using SmartModels with ModelSim VHDLTo use SmartModels with ModelSim VHDL, follow this procedure:1. Make sure MTI VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 73.2. Map the slm_lib logical library, as shown in the following example:% vlib slm_lib% vmap slm_lib slm_libThis step also creates a modelsim.ini file in the current working directory.3. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100psOctober 6, 2003 Synopsys, Inc. 75

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideThen uncomment the libsm and libswift lines corresponding to the platform you areusing:; ModelSim’s interface to Logic Modeling’s SmartModel SWIFT software;libsm = $MODEL_TECH/libsm.sl; libsm = $MODEL_TECH/libsm.dll; Logic Modeling’s SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling’s SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling’s SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling’s SmartModel SWIFT software (Sun4 SunOS); do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib; and run "vsim.swift".; ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll; Logic Modeling's SmartModel SWIFT software (HP64); libswift = $LMC_HOME/lib/hp64.lib/libswift.sl; Logic Modeling's SmartModel SWIFT software (Sparc64); libswift = $LMC_HOME/lib/sparc64.lib/libswift.so4. To create the SmartModel Library VHDL wrappers or templates, run the ModelSimsm_entity script with any optional arguments. The sm_entity script takesSmartModel names as input and writes the VHDL output to STDOUT. You canredirect the output to a file. Run sm_entity as follows. For more information, referto “sm_entity Command Reference” on page 79.% sm_entity -c model > model.vhdFor example:% sm_entity -c ttl373 > ttl373.vhdgenerates the following VHDL file, which has both entity and componentdeclarations for the model. Edit the resulting VHDL file to add the portions of textthat are highlighted in the following example:library IEEE;use IEEE.std_logic_1164.all;entity ttl373 isgeneric ( TimingVersion : STRING := "SN74LS373";DelayRange : STRING := "MAX";ModelMapVersion : STRING := "01008" );port ( C : in std_logic;D1 : in std_logic;D2 : in std_logic;D3 : in std_logic;D4 : in std_logic;D5 : in std_logic;D6 : in std_logic;76 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys ModelsD7 : in std_logic;D8 : in std_logic;OC : in std_logic;Q1 : out std_logic;Q2 : out std_logic;Q3 : out std_logic;Q4 : out std_logic;Q5 : out std_logic;Q6 : out std_logic;Q7 : out std_logic;Q8 : out std_logic );end;architecture SmartModel of ttl373 isattribute FOREIGN : STRING;attribute FOREIGN of SmartModel : architecture is "sm_init$MODEL_TECH/libsm.sl ; ttl373";beginend SmartModel;library ieee; use ieee.std_logic_1164.all; package comp iscomponent ttl373generic ( TimingVersion : STRING := "SN74LS373";DelayRange : STRING := "MAX";ModelMapVersion : STRING := "01008" );port ( C : in std_logic;D1 : in std_logic;D2 : in std_logic;D3 : in std_logic;D4 : in std_logic;D5 : in std_logic;D6 : in std_logic;D7 : in std_logic;D8 : in std_logic;OC : in std_logic;Q1 : out std_logic;Q2 : out std_logic;Q3 : out std_logic;Q4 : out std_logic;Q5 : out std_logic;Q6 : out std_logic;Q7 : out std_logic;Q8 : out std_logic );end component;end comp;5. Compile the model.vhd into a library called slm_lib, as follows:% vcom -93 -work slm_lib model.vhdOctober 6, 2003 Synopsys, Inc. 77

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration Guide6. Instantiate the SmartModel component in your testbench by specifying the requiredSWIFT parameters in the generic map. Here is an example instantiation for theTTL373 model, with the library and use statements, the instance (U1), and theTimingVersion and DelayRange options specified in the generic map for theTTL373 SmartModel Library component.Use the SmartModel Library (slm_lib) just as you would use any other VHDLresource library. Here is an example:library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SLM_LIB;use SLM_LIB.COMPONENTS.ALL;entity TestBench isend TestBench;architecture ArchTestBench of TestBench issignal A, B, C: STD_LOGIC;U1 : TTL373 generic map (TimingVersion => "SN74LS373",DelayRange => "Typ")port map (A => D1, B => D2, C => Q1);P1 : processbegin........For more information on SmartModel configuration parameters, refer to “UsingSmartModels with SWIFT Simulators” on page 18.7. Compile the top-level testbench to a work library (MYWORK) as shown in thefollowing example:% vlib MYWORK% vcom -work MYWORK top.vhd8. Invoke the simulator by running vsim, as shown in the following example:% vsim -lib MYWORK CFGTESTFor information on how to use ModelSim VHDL, refer to the “ModelSim User’sManual.” Note, the design name or configuration name does not necessarily have tobe CFGTEST.78 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Modelssm_entity Command ReferenceThe command reference for sm_entity is as follows.Syntaxsm_entity [options] [SmartModels]Arguments-readRead SmartModel names from standard input.-xeDo not generate entity declarations.-xaDo not generate architecture bodies.-c Generate component declarations.-allSelect all models in the SmartModel Library.-v Display progress messages.By default, sm_entity generates an entity and architecture. Optionally, you can includethe component declaration (-c), exclude the entity (-xe), or exclude the architecture(-xa).Using FlexModels with ModelSim VHDLTo use FlexModels with ModelSim VHDL, follow this procedure.1. Make sure ModelSim VHDL is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 73.2. Map the slm_lib logical library, as shown in the following example:% vlib slm_lib% vmap slm_lib slm_libThis step also creates a modelsim.ini file in the current working directory.3. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100psOctober 6, 2003 Synopsys, Inc. 79

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration Guide4. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxNote, depending on what model you use, the model name may have a “_fz”extension. You must run flexm_setup every time you update your FlexModelinstallation with a new model version. Table 10 describes the FlexModel interfaceand example files that the flexm_setup tool copies.Table 10: FlexModel MTI VHDL FilesFile Name Description Locationmodel_pkg.vhdmodel_user_pkg.vhdmodel_fx_mti.vhdmodel_fz_mti.vhdmodel_fx_comp.vhdmodel_fz_comp.vhdmodel.vhdmodel_tst.vhdModel command procedure calls for HDLCommand Mode.Clock frequency setup and usercustomizations.A SWIFT wrapper for the UNIX model.Component definition for use with the modelentity defined in the above SWIFT wrapperfile. This is put in a package named“COMPONENTS” when compiled.A bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench. This file assumes thatthe “COMPONENTS” package has beeninstalled in the logical library “slm_lib”.A testbench that instantiates the model andshows how to use basic model commands.workdir/src/vhdl/workdir/src/vhdl/workdir/examples/vhdl/workdir/examples/vhdl/workdir/examples/vhdl/workdir/examples/vhdl/5. Update the clock frequency supplied in the model_user_pkg.vhd file to correspondto the desired clock period for the model. After running flexm_setup, this file islocated in:workdir/src/vhdl/model_user_pkg.vhdwhere workdir is your working directory.6. Add or uncomment the following to your vsystem.ini or modelsim.ini file. Note,keep the positions the same.slm_lib=$LMC_HOME/sim/mti/libVHDL93 = 180 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Models7. Compile the FlexModel VHDL files into logical library slm_lib as follows:% mti_path/bin/vcom -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% mti_path/bin/vcom -work slm_lib $LMC_HOME/sim/mti/src/flexmodel_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/src/vhdl/model_user_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/src/vhdl/model_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model_fx_comp.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model_fx_mti.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model.vhd8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement for the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;9. Instantiate FlexModels in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thesupplied bit-blasted wrapper (model_fx_mti.vhd for UNIX).Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );10. Compile the testbench as shown in the following example:% vcom testbench11. Invoke the ModelSim VHDL simulator as shown in the following example:% vsim designOctober 6, 2003 Synopsys, Inc. 81

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideUsing DesignWare Memory Models withModelSim VHDLDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx).To use DWMM models with ModelSim-VHDL, follow these steps:1. Make sure ModelSim VHDL is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 73.2. Map the slm_lib logical library, as shown in the following example:% vlib slm_lib% vmap slm_lib slm_libThis step also creates a modelsim.ini file in the current working directory.3. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100psThen uncomment the libsm and libswift lines for the platform you are using:; ModelSim’s interface to Logic Modeling’s SmartModel SWIFT software;libsm = $MODEL_TECH/libsm.sl; libsm = $MODEL_TECH/libsm.dll; Logic Modeling’s SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling’s SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling’s SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling’s SmartModel SWIFT software (Sun4 SunOS); do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib; and run "vsim.swift".; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll4. To create the model’s bit-blasted VHDL wrapper, run the ModelSim sm_entityscript, as shown in the following example:% $MTI_HOME/bin/sm_entity -c model_mx > model_mx.vhdThis step generates entity and component declarations for the model.NoteIf you want to use more than one DWMM model in your simulation, refer tothe “sm_entity Command Reference” on page 79.82 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Models5. Edit the generated model_mx.vhd file as follows. In the architecture section, add the“library ieee” line highlighted in the following example:architecture SmartModel of model_mx isattribute FOREIGN : STRING;attribute FOREIGN of SmartModel : architecture is "sm_init$MODEL_TECH/libsm.sl ; model_mx;beginend SmartModel;Also, at the end of the model_mx.vhd file, right after the “end component”statement, add the following highlighted line:end component;end comp;6. Compile the required Synopsys libraries into the slm_lib library, as shown in thefollowing examples:% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/mempro_pkg.vhd7. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;USE SLM_LIB.comp.all;8. Compile the model’s bit-blasted wrapper file (model_mx.vhd) into the slm_liblibrary, as shown in the following example:% vcom -93 -work slm_lib model_mx.vhd9. Create a bused wrapper for the model, as shown in the following example:% $LMC_HOME/bin/vsg -bit2bus vhdl model_mxThis step produces an output file named model_mx_bw.vhd.10. Edit the model_mx_bw.vhd file to add Library and Use statements, as shown in thefollowing example:LIBRARY SLM_LIB;USE SLM_LIB.comp.all;11. Compile the model’s bused wrapper, as shown in the following example:% vlib work% vcom -93 model_mx_bw.vhdOctober 6, 2003 Synopsys, Inc. 83

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideAttentionTo use the bused model wrapper, you must add appropriate componentdeclarations to your testbench or edit a component file already included inyour testbench for multiple SWIFT models, specifying ports and generics asrequired.12. Instantiate the model in your design using either the bit-blasted wrapper(model_mx) or the bused wrapper (model_mx_bw). Define the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can copy the model instantiation directly from the modeldatasheet and paste it into your testbench. Be sure to map signal names in yourdesign to the model’s ports. You can access the model datasheet for yourmodel version using the sl_browser tool ($LMC_HOME/bin/sl_browser).13. Compile your testbench (example assumes you are in its directory):% vcom -93 testbench.vhd14. Invoke MTI VHDL and simulate your design:% vsim testbench_configurationFor information on how to use ModelSim VHDL, refer to the ModelSim User’sManual.Using Hardware Models with ModelSimVHDLTo use hardware models with ModelSim VHDL, follow this procedure:1. Make sure ModelSim VHDL is set up properly, and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 73.2. Add the hardware model install tree to your path variable, as shown in the followingexample:% set path=(/install/sms/bin/your_platform/ $path)84 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Models3. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100ps4. Modify the modelsim.ini or project_name.mpf file to include the hardwaremodeling information. Locate the line:[lmc]Remove the semicolons from the libhm line and the libsfi line you will be changingfor your platform. Provide the correct path for the SFI. For example:; ModelSim's interface to Logic Modeling's hardware modeler SFI softwarelibhm = $MODEL_TECH/libhm.sl; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)libsfi = hardware_model_install_path/lib/platform/libsfi.ext; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000); libsfi = /lib/rs6000/libsfi.a; Logic Modeling's hardware modeler SFI software (Sun4 Solaris); libsfi = /lib/sun4.solaris/libsfi.so; Logic Modeling's hardware modeler SFI software (Sun4 SunOS); libsfi = /lib/sun4.sunos/libsfi.so;; libsfi = /lib/pcnt/lm_sfi.dllwhere ext is “so” for Solaris/SunOS and “a” for AIX, or “sl” for HP-UX.5. Run the hm_entity script to generate a .vhd file for the hardware model as shown inthe following example. For details on hm_entity, refer to “hm_entity CommandReference” on page 86.6. You are now ready to use the model in your simulation.ModelSim VHDL Example Using TILS299 HardwareModelHere is an example that uses the TILS299 hardware model. Follow these steps:1. Put the TILS299 hardware model in the testbench.2. Create a working library directory by invoking vsim -gui and selectingLibrary/Create. This creates a working directory called work.3. Compile the .vhd files, as shown in the following example:% vcom -work work TILS299.vhd TB_TILS299.vhdThis step compiles the two VHDL files and puts them in the specified work library.Note that the TILS299.vhd file must be specified first or you get an error becausethe TB_TILS299.vhd utilizes the TILS299 entity.October 6, 2003 Synopsys, Inc. 85

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration Guide4. Invoke the simulator as shown in the following example:% vsim5. When the window comes up, select the testbench to load.6. Use the View/Wave pull-down menu to get the wave window. In the wave window,use File/Load Format wave.do to get the waveforms. After the waveform viewercomes up and the vsim prompt appears, enter “run 10000".7. You can also use some of the hardware model utilities listed below, but thecommands must be entered at the simulator command prompt because they are notVHDL statements. For the TILS299 example, you can also put these commands intothe .do file. Here is an example wave.do file:lm_vectors on /tb_tils299/U0 TEST.VECadd wave -logic {/clk}add wave -logic {/clr}add wave -logic {/s1}add wave -logic {/s0}add wave -logic {/g1}add wave -logic {/g2}add wave -logic {/sr}add wave -logic {/sl}add wave -logic {/qa}add wave -logic {/qh}add wave -literal {/t}hm_entity Command ReferenceThe hm_entity script creates .vhd files for hardware models.Syntaxhm_entity [options] shell_software_filenameArguments-xeDo not generate entity declaration.-xaDo not generate architecture body.-c Generate component declaration-93 Use extended identifiers where needed86 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys ModelsExampleFor example, the following hm_entity invocation:% hm_entity TILS299.MDL > TILS299.vhdgenerates a .vhd file that looks like the following:library ieee;use ieee.std_logic_1164.all;entity TILS299 isgeneric( DelayRange : STRING := "Max" );port ( G2 : in std_logic;CLR : in std_logic;SR : in std_logic;CLK : in std_logic;S0 : in std_logic;G1 : in std_logic;SL : in std_logic;S1 : in std_logic;QA : out std_logic;QH : out std_logic;H : inout std_logic;E : inout std_logic;G : inout std_logic;A : inout std_logic;C : inout std_logic;B : inout std_logic;F : inout std_logic;D : inout std_logic );end;architecture Hardware of TILS299 isattribute FOREIGN : STRING;attribute FOREIGN of Hardware : architecture is "hm_init$MODEL_TECH/libhm.sl; TILS299.MDL";beginend Hardware;October 6, 2003 Synopsys, Inc. 87

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideModelSim VHDL UtilitiesThe following hardware modeler simulator commands are supported in ModelSimVHDL:lm_vectors on | off instance_name filenameThe lm_vectors utility turns on vector logging for the hardware model instance. Thevectors record stimulus to the input and I/O pins and responses from the output and I/Opins during simulation.lm_measure_timing on | off instance_name filenameThe lm_measure_timing utility causes the modeler to measure timing between an inputtransition and resulting output transition on the hardware model. Note that this is onlysupported on LM-family systems.lm_timing_checks on | off instance_nameThe lm_timing_checks utility allows you to enable or disable timing checks such assetups and holds.lm_loop_patterns on | off instance_nameThe lm_loop_patterns utility causes the hardware modeler to continually replay thepattern history of a specified device instance.lm_unknowns on | off instance_nameThe lm_unknowns utility turns off unknown propagation. This “on_unknown” featureis also in the .OPT file for hardware models. It modifies the system's default handling ofdevice input and I/O pins that are set to unknown by the simulator. This utility does notturn on unknown propagation unless it is also turned on in the .OPT file, but it canoverride the setting in the .OPT file to turn this feature off when it is set to on in the.OPT file.88 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models5Using NC-Verilog withSynopsys ModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with NC-Verilog. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 89● “Using SmartModels with NC-Verilog” on page 91● “Using FlexModels with NC-Verilog” on page 92● “Using DesignWare Memory Models with NC-Verilog” on page 95● “Using Hardware Models with NC-Verilog” on page 97Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases, the procedures in this chapter include steps for settingadditional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installationOctober 6, 2003 Synopsys, Inc. 89

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide2. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list (UNIX) orsemicolon-separated list to specify the search path in your variable setting.CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.3. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.4. Set the CDS_INST_DIR variable to the location of your Cadence installation tree,as shown in the following example, and make sure that NC-Verilog is set upproperly in your environment:% setenv CDS_INST_DIR path_to_Cadence_installation5. Depending on your platform, set your load library variable to point to the platformspecificdirectory in $LMC_HOME, as shown in the following examples:Solaris 32-bit:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib: \$CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATHFor Sparc64:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sparc64.lib: \$CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib: \$CDS_INST_DIR/tools/lib:$LD_LIBRARY_PATH90 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys ModelsAIX:% setenv LIBPATH $LMC_HOME/lib/ibmrs.lib: \$CDS_INST_DIR/tools/lib:$LIBPATHHP-UX 32-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$CDS_INST_DIR/tools/lib: \$SHLIB_PATHHP-UX 64-bit% setenv SHLIB_PATH $LMC_HOME/lib/hp64.lib:$CDS_INST_DIR/tools/lib: \$SHLIB_PATHRunning 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.Using SmartModels with NC-VerilogSmartModels work with NC-Verilog using a PLI application called LMTV that isdelivered in the form of a swiftpli shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. Instantiate SmartModels in your design, defining the ports and defparams asrequired. For details on required SmartModel SWIFT parameters and modelinstantiation examples, refer to “Using SmartModels with SWIFT Simulators” onpage 18.3. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.October 6, 2003 Synopsys, Inc. 91

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide4. To use the swiftpli shared library, invoke the NC-Verilog simulator to compile andsimulate your design as shown in the following examples:UNIX% ncverilog testbench model.v +loadpli1=swiftpli:swift_boot \+incdir+$LMC_HOME/sim/pli/src \+ncaccess+r+w5. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var6. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v model.v \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchFor information on LMTV commands that you can use with SmartModels onNC-Verilog, refer to “LMTV Commands” on page 271.Using FlexModels with NC-VerilogFlexModels work with NC-Verilog using a PLI application called LMTV that isdelivered in the form of a swiftpli shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.92 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models2. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 11 lists the files that flexm_setup copies to yourworking directory.Table 11: FlexModel NC-Verilog FilesFile Name Description Locationmodel_pkg.incVerilog task definitions for FlexModelinterface commands. This file also referencesthe flexmodel_pkg.inc andmodel_user_pkg.inc files.workdir/src/verilog/model_user_pkg.inc Clock frequency setup and user customizations. workdir/src/verilog/model_fx_vxl.vmodel.vmodel_tst.vA SWIFT wrapper that you can use to instantiatethe model.A bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench.A testbench that instantiates the model and showshow to use basic model commands.workdir/examples/verilog/workdir/examples/verilog/workdir/examples/verilog/3. Update the clock frequency supplied in the model_user_pkg.inc file to correspondto the CLK period you want for the model. This file is located in:workdir/src/verilog/model_user_pkg.incwhere workdir is your working directory.4. Add the following line to your Verilog testbench to include FlexModel testbenchinterface commands in your design:`include "model_pkg.inc"NoteBe sure to add model_pkg.inc within the module from which you will beissuing FlexModel commands.Because the model_pkg.inc file includes references to flexmodel_pkg.inc andmodel_user_pkg.inc, you don’t need to add flexmodel_pkg.inc ormodel_user_pkg.inc to your testbench.October 6, 2003 Synopsys, Inc. 93

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide5. Instantiate FlexModels in your design, defining the ports and defparams as required(refer to the example testbench supplied with the model). You use the supplied buslevelwrapper (model.v) in the top-level of your design to instantiate the suppliedbit-blasted wrapper (model_fx_vxl.v).Example using bus-level wrapper (model.v) without timing:model U1 ( model ports )defparamU1.FlexModelId = “TMS_INST1”;Example using bus-level wrapper (model.v) with timing:model U1 ( model ports )defparamU1.FlexTimingMode = `FLEX_TIMING_MODE_ON,U1.TimingVersion = “timingversion“,U1.DelayRange = “range“,U1.FlexModelId = “TMS_INST1”;6. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.7. Invoke the NC-Verilog simulator to compile and simulate your design as shown inthe following examples:UNIX% ncverilog testbench +loadpli1=swiftpli:swift_boot \./workdir/examples/verilog/model.v \./workdir/examples/verilog/model_fx_vxl.v \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \\+ncaccess+r+w8. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var94 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models9. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v \./workdir/examples/verilog/model.v \./workdir/examples/verilog/model_fx_vxl.v \-incdir $LMC_HOME/sim/pli/src \-incdir ./workdir/src/verilog% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchFor information on LMTV commands that you can use with FlexModels on NC-Verilog,refer to “LMTV Commands” on page 271.Using DesignWare Memory Models withNC-VerilogDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels, and have an _mx extension (for example, model_mx). DWMM models workwith NC-Verilog using a PLI application called LMTV that is delivered in the form of aswiftpli shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.3. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.4. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxOctober 6, 2003 Synopsys, Inc. 95

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration GuideThis step produces a bused Verilog wrapper file named model_mx_bw.v.5. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).6. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.7. Invoke NC-Verilog to compile and simulate your design, as shown in the followingexample:% ncverilog \model_mx.v \model_mx_bw.v \testbench.v \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w8. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var96 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models9. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib model_mx.v model_mx_bw.v tsetbench.v \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchFor information on LMTV commands that you can use with DWMM models onNC-Verilog, refer to “LMTV Commands” on page 271.Using Hardware Models with NC-VerilogThis section explains how to use Release 3.5a of ModelAccess for Verilog to interfacehardware models with NC-Verilog. You do not need to edit and use the Makefile.nc tobuild a standalone version of the simulator to link to the hardware modeler. Note thatdynamic linking is supported only on version 2.8 and above of NC-Verilog on HP-UXand Solaris.1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.3. Set your SHLIB_PATH or LD_LIBRARY_PATH variable to point to the directoriesthat contain the ModelAccess libraries. Solaris users also need to add the/usr/dt/lib and /usr/openwin/lib libraries.HP-UX% setenv SHLIB_PATH \hardware_model_iinstall_path/sms/ma_verilog/lib/pa_hp102:$CDS_INST_DIR/tools/libSolaris% setenv LD_LIBRARY_PATH \hardware_model_install_path/sms/ma_verilog/lib/sun4.solaris:\$CDS_INST_DIR/tools/lib:/usr/dt/lib:/usr/openwin/lib4. Invoke the simulator as shown in the following example:% ncverilog testbench.v model.v +loadpli1=mav:mav_bootOctober 6, 2003 Synopsys, Inc. 97

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration GuideNC-Verilog Utilities SummaryThe following hardware model utilities are supported in NC-Verilog:$lm_log_test_vectors (“instance_path”, on_off, “filename”)The $lm_log_test_vectors command enables test vector logging for a specified instance,and specifies a file name for the test vector log.$lm_loop_instance (“instance_path”)The $lm_loop_instance command enables the loop mode for a specified model instance.For a detailed syntax description, refer to “$lm_loop_instance Command Reference” onpage 100.$lm_timing_information (“instance_path”, “timing_option”)The $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance. For a detailedsyntax description, refer to “$lm_timing_information Command Reference” onpage 101.$lm_timing_measurements (“instance_path”, on_off, “filename”)The $lm_timing_measurements command enables timing measurements for a specifiedmodel instance. It is not supported for ModelSource 3200 and 3400. For a detailedsyntax description, refer to “$lm_timing_measurements Command Reference” onpage 102.$lm_unknowns (“option=value” [,”option=value”,...] [, “device_or_pin”])The $lm_unknowns command lets you override the hardware modeler’s defaulthandling of unknown values for specified instances or pins, or for all hardware modelinstances in the simulation. For a detailed syntax description, refer to “$lm_unknownsCommand Reference” on page 103.98 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys ModelsNC-Verilog Utilities Reference Pages$lm_log_test_vectors Command ReferenceThe $lm_log_test_vectors command enables test vector logging for a specified instance,and specifies a file name for the test vector log.Syntax$lm_log_test_vectors (“instance_path”, on_off, “filename”)Argumentsinstance_pathon_offfilenameSpecifies the pathname of the model instance for which testvector logging is to be enabled or disabled.Indicates whether test vector logging is to be enabled ordisabled. Allowed values are 1 to enable logging, or 0 (thedefault) to disable logging.Specifies the file name to be used for the test vector log.DescriptionEnables test vector logging for a specified instance and specifies a filename for the testvector log. By default, test vector logging is not performed. When test vector logging ison, the pin value information created during the simulation for the specified deviceinstance is written in test vector file format to filename.For detailed information about test vector logging, refer to the ModelSource User’sManual or the LM-family Modeler Manual.ExampleThe following example enables test vector logging for the instance “U1”, and saves thetest vector log in the file “U1.log”.$lm_log_test_vectors (“Tbench.U1”, 1, “U1.log”);October 6, 2003 Synopsys, Inc. 99

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide$lm_loop_instance Command ReferenceThe $lm_loop_instance command enables the loop mode for a specified model instance.Syntax$lm_loop_instance (“instance_path”)Argumentsinstance_pathSpecifies the pathname of the model instance for which theloop mode is to be enabled.DescriptionEnables the loop mode for a specified instance. In loop mode, the hardware modelerrepeatedly plays to the physical device the pattern history of the specified deviceinstance. This command is most often used to analyze the behavior of a device and itspattern history with an oscilloscope or logic analyzer connected to the device.Once in loop mode, the interface prompts you to press the Return key to exit the loopmode.ExamplesThe following example turns on loop mode for the “U1” model instance.$lm_loop_instance ( “U1” );The following message is displayed while the instance is in loop mode.Entering loop mode for hardware model instance U1Press Return to terminate loop mode.100 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models$lm_timing_information Command ReferenceThe $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance.Syntax$lm_timing_information (“instance_path”, “timing_option”);Argumentsinstance_pathtiming_optionSpecifies the Verilog pathname of the instance whose timinginformation is to be modified.Allowed values are “nodelay” to ignore all delay information,“delay” to process all delay information, “notimingchecks” toignore all timing checks, and “timingchecks” to apply alltiming checks. The defaults are “delay” and “timingchecks”.DescriptionThe $lm_timing_information command allows you to override the hardware modeler’sdefault handling of timing information for a specified model instance. By default, thehardware modeler processes all delay information and applies all timing checks. Youcan decrease model evaluation time by disabling these activities. The hardware modelerdoes not process information that is not needed by the simulator.ExampleThe following example disables timing checks for the “U1” model instance.$lm_timing_information (“U1”, “notimingchecks”);October 6, 2003 Synopsys, Inc. 101

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide$lm_timing_measurements Command ReferenceThe $lm_timing_measurements command enables timing measurements for a specifiedmodel instance. It is not supported for ModelSource 3200 and 3400.Syntax$lm_timing_measurements (“instance_path”, on_off, “filename”)Argumentsinstance_pathon_offfilenameSpecifies the pathname of the model instance for which timingmeasurement is to be enabled or disabled.Indicates whether test vector logging is to be enabled ordisabled. Allowed values are 1 to enable logging, or 0 (thedefault) to disable logging.Specifies the file name to be used for the test vector log.DescriptionThe $lm_timing_measurements command enables timing measurement for a specifiedmodel instance. By default, timing measurement is not performed. Instead, thehardware modeler uses the delay values provided in the .DLY file in the Shell Software.When timing measurement is enabled, the hardware modeler returns to the simulatorand logs to the specified file the actual delays measured from the device.ExampleThe following example enables timing measurements for the”U1” model instance andsaves the timing measurement log in the “U1.log” file.$lm_timing_measurements ( “Tbench.U1”, 1, “U1.log”);102 Synopsys, Inc. October 6, 2003

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models$lm_unknowns Command ReferenceThe $lm_unknowns command lets you override the hardware modeler’s defaulthandling of unknown values for specified instances or pins, or for all hardware modelinstances in the simulation.Syntax$lm_unknowns (“option=value” [,”option=value”,...] [, “device_or_pin”])ArgumentsYou can use the following values for “option=value”:propagate=yes | noWhen “yes” (the default), enables the “on_unknownpropagate” statement, if there is one, in the model’s optionsfile (for example, TILS299.OPT) for the specified instance orpin, or for all hardware model instances in the simulation. Setpropagate=no if you want to disable or override the“on_unknown propagate” statement in the .OPT file for aspecific instance or pin.NoteIf there is no “on_unknown propagate” statement in the model’s .OPT file,unknown propagation is disabled even if you use” $lm_unknownspropagate=yes”. For the “propagate=yes” option to have an effect, theremust be an “on_unknown propagate” statement in the model’s .OPT file. Formore information about the on_unknown statement, refer to the ShellSoftware Reference Manual.value=previous | high | low | floatSpecifies the value to be passed to the device when anunknown value is passed to the modeler. The default is“previous”, meaning that if the simulator sets an input pin to“unknown”, the modeler drives the input to its previous value.For more information, refer to the description of set_previousin the on_unknown reference pages in the Shell SoftwareReference Manual.sequence_count=num_sequencesSpecifies the number of random sequences to propagateunknowns through the hardware model. The num_sequencessetting is an integer of value 0 (the default) through 20. TheOctober 6, 2003 Synopsys, Inc. 103

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guidedefault value, 0, is usually sufficient; setting a higher valueensures that unknowns will be propagated, but uses morepattern memory.random_seed=seed_valueSpecifies the initial seed for the random sequence generator.seed_value is an integer of value 0 (the default) through65535.device_or_pinDescriptionSpecifies the Verilog pathname of a device or pin whoseunknown values are to be translated into the value specified byvalue. The default is to apply the statement to all hardwaremodel instances in the simulation.The $lm_unknowns command lets you override the hardware modeler’s defaulthandling of unknown values for specified model instances or pins, or for all hardwaremodel instances in the simulation. By default, the hardware modeler translates allunknown values to “previous” before passing them to the device. Using this command,you can specify values of high (1), low (0) or float (?), or disable unknown propagation,for a specified instance or pin, or for all hardware model instances in the simulation if noinstance or pin is given. For detailed information about unknown handling, refer to theShell Software Reference Manual.ExamplesThe following example disables unknown propagation and causes a low value to bepassed to the device when an unknown value is passed to the hardware modeler for theinstance “Tbench.U1.”$lm_unknowns (“propagate=no”, “value=low”, “Tbench.U1”)The following example disables unknown propagation, causes a high value to be passedto the device when an unknown value is passed to the modeler, specifies 20 randomsequences to propagate unknowns through the hardware model, and specifies 200 as theseed for the random sequence generator, for all hardware model instances in thesimulation.$lm_unknowns (“propagate=yes”, “value=high”, “sequence_count=20”,“random_seed=200”)104 Synopsys, Inc. October 6, 2003

vSimulator Configuration GuideChapter 5: Using NC-Verilog with Synopsys Modelslmvsg Command ReferenceFor a specified hardware model the lmsvg script creates a model.v file and places it inthe specified destination directory.Syntaxlmvsg [-d destination] [-i] [-w] [-v vector_path] [-h] model.MDLArguments-d destination Specifies the destination directory in which to store thegenerated model.v file. The default is the current directory.-i Generates a warning if a pin name is an illegal Verilogidentifier. By default, no warning is issued.-w Specifies pullup and pulldown signal strength of weak1 andweak0 instead of the default pull1 and pull0, respectively.This will provide compatibility with Cadence's hardwaremodeler interface.-v vector_path Specifies the pathname to the file containing a list of vectors.-h Displays the online help for this command.model.MDLSpecifies the name of the MDL file of the hardware modelwhose model.v file is to be generated.DescriptionThe lmvsg script creates a model.v, in the destination directory. The model’s pin namesmay not be legal Verilog identifiers. If a pin name is found that is not a legal Verilogidentifier, lmvsg escapes the illegal name (for example, the pin name “-CLR” becomes“\-CLR”.) and, if the -i switch was issued, displays a warning message.If a pin alias is defined in the model.NAM file, the pin alias is used as the pin name. Forinformation about editing the model.NAM file, refer to the ModelSource User’s Manual.By default, lmvsg generates a module that contains a port for each logical pin. If youwant the module to use vectors for buses, you can provide a file containing a list of thevectors. For example, if a device contains a 32-bit address bus, the default behavior oflmvsg is to generate a module with a port list containing the ports A0, A1, ..., A31. Youcan use the -v switch to name a file containing the statement “A[31:0]”. lmvsg thengenerates the module using a 32-bit vector for the address bus.October 6, 2003 Synopsys, Inc. 105

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Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys Models6Using NC-VHDL with SynopsysModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with NC-VHDL. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 107● “Using SmartModels with NC-VHDL” on page 109● “Using FlexModels with NC-VHDL” on page 110● “Using DesignWare Memory Models with NC-VHDL” on page 114● “Using Hardware Models with NC-VHDL” on page 120NoteCadence’s NC-VHDL simulator does not support on any platform C-Flexbased FlexModels when the control language is Vera. Cadence is aware ofthe problem and plans a future fix.Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases the procedures that follow in this chapter include steps forsetting additional environment variables.October 6, 2003 Synopsys, Inc. 107

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installation2. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, FlexModels andDesignWare Memory Models) into the same authorization file. If you need to keepseparate authorization files for different products, use a colon-separated list(UNIX).CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.3. Make sure that NC-VHDL is set up properly in your environment. See the NC-VHDL Simulator Configuration Guide for details.4. Depending on your platform, set your load library variable to point to the platformspecificdirectory in $LMC_HOME, as shown in the following examples:Solaris 32-bit:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATHAIX:% setenv LIBPATH $LMC_HOME/lib/ibmrs.lib:$LIBPATHHP-UX 32-bit:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$SHLIB_PATHSPARC64% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sparc64.lib:$LD_LIBRARY_PATHHP64% setenv SHLIB_PATH $LMC_HOME/lib/hp64.lib:$SHLIB_PATH108 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys ModelsRunning 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.Using SmartModels with NC-VHDLTo use SmartModels with NC-VHDL, follow this procedure:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. Add the following line to your cds.lib file to specify the logical library sm_libraryfor SmartModels, as shown in the following example:DEFINE sm_library ./sm_library3. Run the ncshell utility to generate a wrapper for the model that you want to use, asshown in the following example:% ncshell -import swift -into vhdl model -nocompile -work sm_libraryThis step produces a wrapper file (model.vhd) and a component declaration(model_comp.vhd) for the specified model in the sm_library work directory.If you want to generate wrappers for all SmartModels in your $LMC_HOME tree,add the -all switch to the ncshell invocation. In this case, ncshell creates one file(shell.vhd) that contains all the model wrappers and another file (component.vhd)that contains the component declarations.4. Add LIBRARY and USE statements to your testbench:library sm_library;use sm_library.component.all;5. Instantiate SmartModels in your design using the wrapper files that you generated inStep 3. For information on required configuration parameters and instantiationexamples, refer to “Using SmartModels with SWIFT Simulators” on page 18.October 6, 2003 Synopsys, Inc. 109

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide6. Compile the other VHDL files into the work library, as shown in the followingexample:% ncvhdl -w work testbench.vhd7. Elaborate your design as shown in the following example:% ncelab cfgtest8. Set the LMC_TIMEUNIT environment variable to -12 for 1 ps resolution, as shownin the following example:% setenv LMC_TIMEUNIT -12This sets a global timing resolution for all SWIFT models in your simulation. Formore information on the LMC_TIMEUNIT environment variable, refer to theCadence documentation for NC-VHDL.9. Invoke the NC-VHDL simulator on your design as shown in the following example:% ncsim designUsing FlexModels with NC-VHDLTo use FlexModels with NC-VHDL, follow this procedures:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. If you have built your own Foreign Model Interface (FMI) shared library or youhave another third party FMI, perform this step.AttentionIf you do not build your own FMI library, skip to Step 3.NC-VHDL binds in only one shared FMI library at runtime. If your design usesFMI, you need to build a new FMI shared library that contains your library and theFlexModel library. A FlexModel archive library can be found at:HP-UX 32 and 64 bits:$LMC_HOME/lib/hp700.lib/libfmi_ar.a$LMC_HOME/lib/hp64.lib/libfmi_ar.aSolaris 32 and 64 bits:$LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.a$LMC_HOME/lib/sparc64.lib/libfmi_ar.a110 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys ModelsYou must create a new archive that includes the FlexModel archive, library table filedeclaration object file, and your archive. Detailed instructions for this process canbe found in the “Foreign Model Integration” chapter of the Affirma NC VHDLSimulator C Interface User Guide.As shown in the following example, you must combine the contents of theFlexModel library table file with your own FMI application library table. If you donot have a table, create a new C file that contains the information shown below.#include extern fmiModelTableT CpipeModelTable;fmiLibraryTableT fmiLibraryTable = {{"Cpipe", CpipeModelTable},{0, 0}};For our example we will call this C file, new_FMI_table.c.If you already have a file defining fmiLibraryTable, include these two lines at theappropriate locations in the C file:extern fmiModelTableT CpipeModelTable;{"Cpipe", CpipeModelTable},Link the FlexModel archive library with the new library table object file and anyother FMI application object files you wish to include, following the instructions inthe Cadence C Interface User Guide.The following examples show compiling the library table object files and linkingFlexModel libfm_ar.a with the library table object file and the FMI application youdeveloped, shown in the examples as new_FMI_table.o and your_archive.a:HP-UX (32 bit example)% /bin/cc -D_NO_PROTO -c +Z -I$CDS_VHDL/include new_FMI_table.c% /bin/ld -b -o libfmi.sl new_FMI_table.o your_archive.a \$LMC_HOME/lib/hp700.lib/libfmi_ar.aSolaris% /opt/SUNWspro/bin/cc -c -KPIC -I$CDS_VHDL/include new_FMI_table.c% /opt/SUNWspro/bin/cc -G -o libfmi.so new_FMI_table.o \your_archive.a $LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.a3. Add the following lines to your cds.lib file:define slm_lib slm_lib_pathdefine work work_lib_pathOctober 6, 2003 Synopsys, Inc. 111

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide4. Generate a VHDL wrapper file for the model by invoking ncshell, as shown in thefollowing example:% ncshell -import swift -into vhdl model_fx -nocompile -work slm_lib5. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 12 describes the FlexModel NC-VHDL interface andexample files that the flexm_setup tool copies.Table 12: FlexModel NC-VHDL FilesFile Name Description Locationmodel_pkg.vhdModel command procedure calls for HDLCommand Mode.workdir/src/vhdl/model_user_pkg.vhd Clock frequency setup and usercustomizations.workdir/src/vhdl/model_fx_comp.vhdmodel.vhdmodel_tst.vhdComponent definition for use with the modelentity defined in the SWIFT wrapper file. Thisis put in a package named “COMPONENTS”when compiled.A bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench. This file assumes thatthe “COMPONENTS” package has beeninstalled in the logical library “slm_lib”.A testbench that instantiates the model andshows how to use basic model commands.workdir/examples/vhdl/workdir/examples/vhdl/workdir/examples/vhdl/6. Update the clock frequency supplied in the model_user_pkg.vhd file in yourworking directory to correspond to the desired clock period for the model. After yourun flexm_setup this file is located in:workdir/src/vhdl/model_user_pkg.vhdwhere workdir is your working directory.7. Create a logical library named slm_lib. The default physical library mapping for thisis $LMC_HOME/sim/simulator/lib; however, you can put the physical libraryanywhere you want.112 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys Models8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement for the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;9. Instantiate FlexModels in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thebit-blasted wrapper generated in Step 3 (model_fx.vhd) using ncshell.Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );10. Compile the FlexModel VHDL files into logical library slm_lib as follows:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhd% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/flexmodel_pkg.vhd% ncvhdl -w slm_lib workdir/src/vhdl/model_user_pkg.vhd% ncvhdl -w slm_lib workdir/src/vhdl/model_pkg.vhd% ncvhdl -w slm_lib workdir/examples/vhdl/model_fx_comp.vhd% ncvhdl -w slm_lib model_fx.vhd% ncvhdl -w slm_lib workdir/examples/vhdl/model.vhd% ncvhdl-w work testbench11. Elaborate your design as shown in the following example:% ncelab cfgtestOctober 6, 2003 Synopsys, Inc. 113

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide12. Set the LMC_TIMEUNIT environment variable to -12 for 1 ps resolution, as shownin the following example:% setenv LMC_TIMEUNIT -12This sets a global timing resolution for all SWIFT models in your simulation. Formore information on the LMC_TIMEUNIT environment variable, refer to theCadence documentation for NC-VHDL.13. Invoke the NC-VHDL simulator as shown in the following example:% ncsim designUsing DesignWare Memory Models withNC-VHDLDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx).To use DWMM models with NC-VHDL, follow these steps:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. Edit your cds.lib file to specify the logical library slm_lib for DWMM models:DEFINE slm_lib ./slm_libNoteAlso, make sure your cds.lib and hdl.var files contain the correctSOFTINCLUDE statements for running NC-VHDL.3. Create a directory named slm_lib:mkdir slm_lib4. Compile the required Synopsys libraries into the slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhdNoteIgnore the warning: ncvhdl_p: *W,FATSPB (slm_hdlc.vhd,72).% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd114 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys ModelsAttentionYou can omit steps 5 and 6, below, if you already performed those tasks asdescribed in “Using SmartModels with NC-VHDL” on page 109.5. Run the ncshell utility to generate a wrapper for the model you want to use:% ncshell -import swift -into vhdl model_mx -nocompile -work slm_libThis step produces in the slm_lib work directory a bit-blasted wrapper file(model_mx.vhd) and a component declaration file (model_mx_comp.vhd) for thespecified model.6. Compile the bit-blasted wrapper and component file:% ncvhdl -w slm_lib model_mx.vhd% ncvhdl -w slm_lib model_mx_comp.vhd7. If you want to use a bused wrapper for the model, do the following:a. Use the following command to produce a bused wrapper file namedmodel_mx_bw.vhd:% $LMC_HOME/bin/vsg -bit2bus vhdl model_mxb. Edit the model_mx_bw.vhd file to add Library and Use statements to the top ofthe file:LIBRARY SLM_LIB;USE SLM_LIB.smartmodels.all;c. Compile the bused wrapper:% ncvhdl -w slm_lib model_mx_bw.vhdAttentionIf you want to use the bused model wrapper, you must add appropriatecomponent declarations to your testbench or edit a component file alreadyincluded in your testbench for multiple SWIFT models, specifying ports andgenerics as required.8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.smartmodels.all;use slm_lib.mempro_pkg.all;October 6, 2003 Synopsys, Inc. 115

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide9. Instantiate the model in your design using the bused wrapper (model_mx_bw) or thebit-blasted wrapper (model_mx). Define the ports, testbench pins, and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters, though you can override these values in your testbench ifneeded.For details on the required SWIFT parameters and DWMM instantiation examples,see “DesignWare Memory Model SWIFT Parameters” on page 29.Here is an example of a typical bused wrapper file:PORT MAP (a => sm_a,cs_n => sm_cs_n,be_n => sm_be_n,io => sm_io,oe_n => sm_oe_n,we_n => sm_we_n);SIGNAL sm_a : STD_LOGIC_VECTOR(17 DOWNTO 0);SIGNAL sm_cs_n : STD_LOGIC;SIGNAL sm_be_n : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_io : STD_LOGIC_VECTOR(16 DOWNTO 1);SIGNAL sm_oe_n : STD_LOGIC;SIGNAL sm_we_n : STD_LOGIC;SIGNAL sm_dout_valid : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_wr_data : STD_LOGIC_VECTOR(0 TO 15);HintFor model-specific instantiation examples, see the model datasheets. Youcan cut and paste the instantiation directly from the model datasheet and intoyour testbench. Be sure to map signal names in your design to the model’sports. You can access the model datasheet for your version of the model withthe sl_browser tool ($LMC_HOME/bin/sl_browser).116 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys ModelsAttentionFor best performance, use version 4.0 or later of NC-VHDL. NC-VHDLversion 4 and higher allow you to load multiple dynamic libraries containingC code. To use this means of loading the DWMM routines, include thefollowing option in the line invoking ncsim:ncsim -loadfmi libfmi_ml.so:slm_boot libfmi_ml.so (or .sl on HP-UX platforms) contains the library table andbootstrap function needed by the dynamic loader included in NC-VHDLversion 4.0 and above. This method eliminates the need to link libfmi_ar.awith your other external C (foreign language) modules to produce a singlelibfmi.so that incorporates all foreign language modules in a single library.For more information about using the NC-VHDL with multiple dynamiclibraries, see your Cadence simulator documentation.Using VERA and DesignWare Memory Models withNC-VHDLIf your NC-VHDL simulation includes DWMM models and VERA, you'll need tocreate a custom libfmi.so file.NoteNC-VHDL allows the bodies of VHDL entities and functions to be writtenin C and dynamically linked with the simulation executable at run time. AllC code must be in a single dynamic library named libfmi.so (solaris) orlibfmi.sl (HP-UX), and there must be a single fmiLibraryTable array in thelibfmi dynamic library file. The fmiLibraryTable contains the mapping ofVHDL element names to C code names, and must contain one entry for eachVHDL element to C code mapping.When combining C code for multiple products such as VERA, DWMMmodels, other vendor’s products, or your own C code, you must create a Csource file containing a fmiLibraryTable with mapping entries for eachproduct. The format of this array is discussed in your Cadence NC-VHDL Cuser document.If you use NC-VHDL version 4.0 or later, we recommend using its multiplefile loading mechanism.October 6, 2003 Synopsys, Inc. 117

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration GuideFor NC-VHDL Version 3 or LowerFollow these steps to create an NC-VHDL (version 3 or lower) compatible libfmi.sodynamic library for use with VERA and DWMM models.1. Create a C source file named sim_user.c in which to put the fmiLibraryTable, orcopy the sim_user.c file from the VERA tree to use as a template:cp $VERA_HOME/lib/nc_vhdl/sim_user.c .2. Add the following lines to the new sim_user.c:#include extern fmiModelTableT vera_mtbl;extern fmiModelTableT CpipeModelTable;/*** Add externs for the fmiModelTables of any other C code modules** included in your custom libfmi.(so|sl) dynamic library*/fmiLibraryTableT fmiLibraryTable = {{ "vera", vera_mtbl }, /* mapping for VERA C code */{ "Cpipe", CpipeModelTable }, /* mapping for DWMM model C code *//*** Add map entries for any other C code modules included in your custom** libfmi.(so|sl) dynamic library. Refer to vendor documentation** to determine the names needed for each product.*/{ 0, 0 }, /* null entry to mark the table end */};3. Compile sim_user.so, as in this example for Solaris:/opt/SUNWspro/bin/cc -c -KPIC -o sim_user.o \-I$CDS_INST_DIR/tools.sun4v/inca/include sim_user.c4. Combine the sim_user.o and object files for each product included in the libfmi.sofile:/opt/SUNWspro/bin/cc -G -o libfmi.so \sim_user.o \${VERA_HOME}/lib/vera_user.o \${VERA_HOME}/lib/libVERA.a \${VERA_HOME}/lib/nc_vhdl/libVERAbr.a${LMC_HOME}/lib/sun4Solaris.lib/libfmi_ar.a118 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys ModelsNoteMake sure there is only one fmiLibraryTable among all the objectscombined into the libfmi.so file. You can use the UNIX nm command (andC shell) to do this:foreach obj ( )nm ${obj} | grep fmiLibraryTableendIf fmiLibraryTable is defined more than once, the libfmi.so will probably beunusable.5. Use NC-VHDL to compile and elaborate your design:% ncvhdl testbench.vhd% ncelab testbench_configuration6. Set the LMC_TIMEUNIT environment variable to -12 for 1 ps resolution:% setenv LMC_TIMEUNIT -12This sets a global timing resolution for all SWIFT models in your simulation. Formore information on the LMC_TIMEUNIT environment variable, refer to theCadence documentation for NC-VHDL.7. Set your LD_LIBRARY_PATH (Solaris) or SHLIB_PATH (HP-UX) environmentvariable so the working directory where you created the new libfmi.(so|sl) is first onthe library directory path list.% setenv LD_LIBRARY_PATH ":${LD_LIBRARY_PATH}"8. Invoke NC-VHDL to simulate your design:% ncsim testbench_configurationFor NC-VHDL Version 4 or HigherFollow these steps to use NC-VHDL (version 4 or higher) with VERA and DWMMmodels.1. Set the dynamic library search path to look first in the VERA library directory, andthen in the LMC_HOME solaris library:% setenv LD_LIBRARY_PATH"${VERA_HOME}/lib/nc_vhdl:${LMC_HOME}lib/sun4Solaris.lib:${LD_LIBRARY_PATH}"2. Use NC-VHDL to compile and elaborate your design:% ncvhdl testbench.vhd% ncelab testbench_configurationOctober 6, 2003 Synopsys, Inc. 119

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration Guide3. Run your simulation:% ncsim -loadfmi libfmi_ml.so:slm_boot NoteIf you include your own or other vendors’ C code in your simulation, youmay need to build a custom libfmi.so as shown above. In this case, do notinclude this line in the libFmiLibrary table:{"Cpipe", CpipeModelTable}The Cpipe (DWMM) code is present in the libfmi_ml.so library loaded fromthe command line. Refer to your Cadence NC-VHDL C user documentationfor details of the -loadfmi ncsim command line switch for loading multipledynamic libraries.Using Hardware Models with NC-VHDLTo use hardware models with NC-VHDL, follow this procedure. For the latestinformation on supported features, refer to the Cadence documentation.1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. Add the hardware model install tree to your path variable, as shown in the followingexample:% set path=(/install/sms/bin/platform/ $path)3. Create your own library directory for files that will be generated for the hardwaremodel.4. Run the ncshell command to generate .vhd wrapper files, as shown in the followingexample:% ncshell -import lmsfi -into vhdl models/TILS299/TILS299.MDLYou can also use the -all switch to create .vhd files for multiple hardware models.NC-VHDL Example with TILS299 Hardware ModelThe following example uses the TILS299 hardware model to show how to set uphardware models for use with NC-VHDL:1. Create a testbench to instantiate the hardware model (for exampleTB_TILS299.vhd).120 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 6: Using NC-VHDL with Synopsys Models2. Run ncvhdl to compile your .vhd files, as shown in the following example:% ncvhdl TILS299.vhd TILS299_comp.vhd TB_TILS299.vhd3. Elaborate the design, as shown in the following example:% ncelab -messages work.tb_tils299:test4. Invoke the NC-VHDL simulator, as shown in the following example:% ncsim -gui work.tb_tils299:testNC-VHDL UtilitiesThe following hardware modeler simulator commands are supported in NC-VHDL:lm_log_test_vectors (“instance_name”, 1/0, “filename”);Enables (1) or disables (0) vector logging for hardware models.lm_timing_measurements (“instance_name”, 1/0, “filename”);Enables (1) or disables (0) timing measurements for hardware models.lm_enable_timing_checks ([device_name(s)....])Enables timing checks for hardware models.lm_disable_timing_checks ([device_name(s)....])Disables timing checks for hardware models.lm_unknowns (“option=value”, ....device_or_pin);Determines how unknown values are handled by hardware models. Supported optionsinclude:●●●●propagate=yes/novalue=previous/high/lowsequence_count=0-20random_seed=0-65535● device_or_pinlm_loop_instance ([instance_name]);Makes the hardware modeler enter loop mode, where it continually replays the patternhistory of the specified instance.lm_pam_shortage(“actions=save/sleep/finish/free/suspend/drop_faults”,”sleep_minutes=n, “sleep_count=n”, “save_file=filename”);October 6, 2003 Synopsys, Inc. 121

Chapter 6: Using NC-VHDL with Synopsys ModelsSimulator Configuration GuideLets you specify the action the hardware modeler is to take when it has used up most ofthe available pattern memory.lm_pattern_history ([device_name(s)....])Saves the pattern memory for a private device instance.ExamplesYou can use any of these utilities by calling them from VHDL code or invoking themfrom the debugger prompt with an lm_procedure call.Example call from VHDL code:Variable ret : Natural;...ret := lm_log_test_vectors(":U1",1,"U1.VEC");wait for 800 ns;ret := lm_log_test_vectors(":U1",0,"U1.VEC");Example invocation from the debugger prompt with lm_procedure call:% ncsim> call lm_log_test_vectors :U0 1 299.VEC122 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models7Using QuickSim II with SynopsysModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with QuickSim II. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 123● “Using SmartModels and FlexModels with QuickSim II” on page 125● “Using DesignWare Memory Models with QuickSim II” on page 151● “Using Hardware Models with QuickSim II” on page 164Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases the procedures that follow in this chapter include steps forsetting additional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel and FlexModel installation tree, as shown in the following example:% setenv LMC_HOME path_to_models_installation2. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileOctober 6, 2003 Synopsys, Inc. 123

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list (UNIX).CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.3. Set MGC_HOME to the location of your Mentor installation, and make sureQuickSim II is set up properly in your environment.% setenv MGC_HOME path_to_Mentor_installation4. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.5. Depending on your platform, set your load library variable to point to yourplatform’s directory in $LMC_HOME, as shown in the following examples:Solaris:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATHLinux:% setenv LD_LIBRARY_PATH $LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATHAIX:% setenv LIBPATH $LMC_HOME/lib/ibmrs.lib:$LIBPATHHP-UX:% setenv SHLIB_PATH $LMC_HOME/lib/hp700.lib:$SHLIB_PATHRunning 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1124 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsThe LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.Using SmartModels and FlexModels withQuickSim IINoteQuickSim II cannot simulate 64-bit FlexModel or 64-bit SmartModels.This section explains how to use SmartModels and FlexModels with QuickSim II. Touse FlexModels with QuickSim II, you use C-only Command Mode. For information onC-only Command Mode, refer to “Using FlexModels with SWIFT Simulators” onpage 23. The rest of this section explains required installation steps and how to usemodel symbols in the schematic capture front-end to the simulator. This information isorganized in the following major subsections:● “Installing the QuickSim II SWIFT Interface” on page 125● “Using SmartModels/FlexModels with QuickSim II” on page 127● “Schematic Capture” on page 127● “Logic Simulation” on page 134● “Custom Symbols” on page 144Installing the QuickSim II SWIFT InterfaceSynopsys ships the part of QuickSim II that communicates with the SWIFT interface forversions of QuickSim II prior to the D.1 release. If you are using a version of QuickSimII prior to D.1, you must install the Mentor Graphics application software for eachMentor Graphics user tree.AttentionBeginning with version D.1 of QuickSim II, Mentor Graphics assumedresponsibility for their integration of the SWIFT interface. If you are usingversion D.1 or higher, refer to the Mentor Graphics documentation forinformation about using SWIFT.October 6, 2003 Synopsys, Inc. 125

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideEvery time you install or update Mentor Graphics application software, you must createa user tree for the SWIFT SmartModel Library. Use the MGC install tool to createduplicate Mentor Graphics user trees. User trees typically require between 10–20 MB ofdisk space. For questions about creating Mentor Graphics user trees, refer to the MentorGraphics documentation. Follow these steps:1. If you are using a version of QuickSim II prior to D1, for each Mentor Graphicshome directory (user or master tree) that requires access to the SWIFT interface,execute the following command:UNIX% $LMC_HOME/bin/mgc_ins -m $MGC_HOME -l $LMC_HOME2. Add “$LMC_HOME” followed by a blank line to your location map file.3. Add SmartModel Library Menus to Design Architect. Normally, as part ofinstallation, the Admin tool automatically adds SmartModel menus to DesignArchitect for the models you installed. Use the instructions in this section to add theSmartModel menus only if, after installation, you do not find SmartModel menuentries under the Design Architect “Libraries” pull-down menu. To includeSmartModel menu selections in the Design Architect (DA) menus, follow thesesteps:a. Set the AMPLE_PATH environment variable. If this variable already exists, useone of these commands as appropriate:UNIX% setenv AMPLE_PATH ${AMPLE_PATH}:$LMC_HOME/special/qsim/menusIf you have a custom userware directory, you can create links that point to“$LMC_HOME/special/qsim/menus/des_arch.”b. If the AMPLE_PATH environment variable does not exist, use one of thesecommands as appropriate:UNIX% setenv AMPLE_PATH $LMC_HOME/special/qsim/menusIf you have a custom userware directory, you can create links that point to“$LMC_HOME/special/qsim/menus/des_arch.”4. Generate the menus as shown in the appropriate example:UNIX% $LMC_HOME/bin/mgc_menu.pl126 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsMenu entries are created for the models that you have installed. If menu entries aremissing for models you believe you have in your library, use the Admin tool to verifyyour installed models. If you change your model installation, rerun mgc_menu to updatethe menu to reflect the new model list.After successful menu activation, the “Libraries” pull-down menu of the SchematicEditor contains an entry for “Logic Modeling SmartModel Library.” If you haveSimuBus models installed, the pull-down menu also contains an entry for “LogicModeling SimuBus Products.”Using SmartModels/FlexModels with QuickSim IIThis chapter provides information about using SmartModels (including FlexModels)with Mentor Graphics (MGC) tools. This information is organized in the followingmajor sections:●●●Schematic CaptureLogic SimulationCustom SymbolsSchematic CaptureAdding a SmartModel Library model to a design schematic involves identifying thedesired symbol, instantiating it, and then editing its properties as necessary. Synopsyssupplies a complete Schematic Editor menu system in the QuickSim II environment thatyou can use to identify and instantiate a component. You can also instantiate symbolsfrom the command line and edit property values interactively using Design Architect.This chapter provides information about both approaches to building a design, followingan introductory discussion of the symbols and their properties.For more information about Design Architect and the Schematic Editor, refer to theMentor Graphics documentation.SymbolsSynopsys provides symbols representing default package pinouts for each SmartModel.Some models have more than one symbol associated with them. This is true for:●●Models of simple logic gates, which are supplied with DeMorgan equivalentnegative logic symbols in addition to standard symbolsModels that offer both pin and bus symbolsFor information about symbol compatibility with different versions of the DesignArchitect software, refer to the SmartModel Library Release Notes.October 6, 2003 Synopsys, Inc. 127

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuidePin and Bus SymbolsFor many high pin-count parts, you get pin and bus symbols. Bus symbols may be moreconvenient to use than their pin equivalents, because they take up less real estate on theschematic and are easier to connect and to read. Figure 2 illustrates the differencesbetween pin and bus symbols.Figure 2: Sample Pin and Bus SymbolsSymbol PropertiesAssigning specific values to symbol properties completes the definition of aSmartModel. The properties used on the symbols provided for the Mentor GraphicsDesign Architect environment include:●●●Symbol properties used by SWIFT interface modelsSymbol properties required for simulationOptional symbol properties128 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsYou can edit symbol property values either with the Schematic Editor pop-up menu orby using the QuickSim II CHANGE TEXT VALUE command. These properties arehidden or visible depending on the visibility attributes selected by your library manager.Figure 3 illustrates the positions of the visible properties on a symbol supplied bySynopsys.Figure 3: Visible Symbol PropertiesSymbol Properties used by SWIFT ModelsTable 13 lists symbol properties that are used by SWIFT interface models.Table 13: Symbol Properties used by SWIFT ModelsPropertyTimingVersionMemoryFileDescriptionTiming version to use with a model. Any valueassigned to the TimingVersion property must be avalid timing version for that model.Name and path of a memory image file.October 6, 2003 Synopsys, Inc. 129

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTable 13: Symbol Properties used by SWIFT Models (Continued)PropertyPCLFileJEDECFileDescriptionName and path of a compiled PCL file.Name and path of a JEDEC fuse map file.NoteFlexModels use a slightly different set of symbol properties. For informationon the required configuration properties for FlexModels, refer to “UsingFlexModels with SWIFT Simulators” on page 23.You can use either an absolute or relative path name to point to a file. If you use arelative path name it is resolved relative to the value of $MGC_WD.Symbol Properties Required for SimulationTable 14 lists symbol properties that are required for simulation.Table 14: Symbol Properties Required for SimulationPropertyMODELPINPINTYPEDescriptionThe MODEL property contains a label registered astype “SWIFT”.Logic simulation requires that each pin on a symbolhave a property. A PIN property has two valuesassociated with it:● User pin name●Compiled pin nameYou can change the user pin name to adhere todrafting standards, but you must not change thecompiled pin name.Each model pin has an associated PINTYPEproperty, which describes the pin entry point type(i.e., IN, OUT, IXO, or IO). QuickSim II requiresthis property.SWIFT_TEMPLATE The SWIFT_TEMPLATE property always has avalue that specifies the model name. This propertycannot be changed.130 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTable 14: Symbol Properties Required for Simulation (Continued)PropertyDescriptionPKGEach model has a PKG property equal to thephysical package type (for example, DIP, LCC) thatthe symbol's pin numbers match. When using thebus symbol for a component, the PKG property isset to the value “BUS”.Optional Symbol PropertiesTable 15 lists optional symbol properties.Table 15: Optional Symbol PropertiesPropertyCOMPPIN_NAMEPIN_NOREFDescriptionThe COMP property provides an interface to layoutor other applications. Synopsys does not use thisproperty.The COMP property is assigned the default value“TimingVersion” with the property attribute“expression”. This causes the COMP property totrack the value of the TimingVersion property forSynopsys symbols.The PIN_NAME property is the visible text on asymbol representing a pin's name. Changing thistext has no effect on the model's operation.The PIN_NO property value matches the physicalpin number of the component for the defaultpackage. Changing the value of this property has noeffect on the model's operation.The REF (reference) property provides an identifierfor use in Advanced Verification messages.Changing the value of this property has no effect onthe model's operation.Building a Design Using the MenusThe Synopsys entries in the Design Architect menu system can be useful when buildinga design for the first time because all of the alternatives at each menu level are apparent.To add SmartModels to a design using the menus, follow these steps:1. Identify the desired model using the Schematic Editor menu system to traverse themenus.October 6, 2003 Synopsys, Inc. 131

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration Guide2. Instantiate the model's symbol on the schematic sheet.3. Edit property values as necessary using Design Architect or the Schematic Editor.The Menu SystemThe menu system consists of several levels, starting with the pull-down menu that isaccessed with the Libraries choice from the Design Architect menu bar. At that point,the following menu choices are available:●●Logic Modeling SmartModel LibraryLogic Modeling SimuBus Products (this entry is present only if you have installedSimuBus models)NoteNormally, the Admin tool installs the Logic Modeling entries in the DesignArchitect Libraries menu automatically, as part of model installation. If,after installing your models, you do not find at least the Logic ModelingSmartModel Library entry, you can perform the menu installation yourself.For more information, refer to “Installing the QuickSim II SWIFT Interface”on page 125.Following are descriptions of the relevant menu levels:Top-levelThe top-level menu offers a number of choices, including component libraries andthe first SmartModel product menu.FunctionThe first SmartModel product menu offers a choice of functions, as follows:❍❍❍❍General purpose logic menuLogic block menuMemories menuProcessor menu❍❍Programmable logic menuSupport peripheral menuSubfunctionEach item on the function menu has its own subfunction menu, which is used tofurther specify the symbol for the model being instantiated.132 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsVendorEach subfunction menu selection has an associated vendor menu, which displays alist of part manufacturers for that subfunctional group of models.PartEach vendor menu selection has an associated part menu, which displays a list ofall SmartModels for the selected subfunction class and vendor.ComponentEach part menu selection has an associated component menu, which displays a listof all the timing and/or symbol versions available for a particular model.ExampleThe following sequence of menu selections activates a Motorola MC88100:SmartModel Library > Processor > Microprocessor > Motorola >88100 > MC88100-20 (BUS)Choosing the function, subfunction, and vendor brings up the part menu, which showsall the Motorola microprocessor models. Choosing the MC88100 brings up thecomponent menu, which shows both the component and the symbol.Building a Design Without the MenusUsers who are familiar with the SmartModel Library may prefer to use Schematic Editorcommands to build designs. This approach can be faster than using the menu system.The basic steps are the same:1. Identify the model you need.2. Instantiate the model's symbol on the schematic sheet.3. Use Design Architect or the Schematic Editor to edit property values, as necessary.Creating An InstanceUse the $add_instance command to instantiate a part in the Schematic Editor, as shownin the following minimal command:% $add_instance (“$LMC_HOME/special/qsim/symbols/”)The symbol name and TimingVersion property value can also be included on the sameline, as follows. (All punctuation marks are required.)% $add_instance \(“$LMC_HOME/special/qsim/symbols/”,“”,,,[“TimingVersion”,””])October 6, 2003 Synopsys, Inc. 133

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideIf the TimingVersion property value is not specified, the default timing version isactivated. If a symbol is not specified when applicable, the default is used. The defaultsare “positive” for logic version, and “pin” for symbol type.Selecting Alternate SymbolsWhen there are DeMorgan equivalent symbols, the positive version is the default.Specify “NEG” as the symbol name to get the negative logic symbol (if desired), asfollows:% $add_instance (“$LMC_HOME/special/qsim/symbols/ttl00”,”NEG”,,, \[“TimingVersion”,”SN74AS00”])When activating parts manually, remember that the pin symbol is the default when bothpin and bus symbols are available. Specify the bus symbol (if desired), as follows:% $add_instance (“$LMC_HOME/special/qsim/symbols/mc68030_hv”,”BUS”,,, \[“TimingVersion”,”MC68030-33”])Use the Mentor Graphics Design Viewpoint Editor (DVE) to set the primitive type forSWIFT in DVE. To ensure that SWIFT instances are evaluated as primitives, you canadd to the primitive rule using the add primitive command within DVE. In the followingexample, the add primitive command causes all instances of the MODEL property value“SWIFT” to be evaluated as primitives by QuickSim II.% add primitive “model” -noexcept -string “SWIFT”The string “SWIFT” can be substituted with any other labels that you have registeredwith the model type of “swift”.Logic SimulationThe following sections in this chapter provide information about using SmartModels forlogic simulation in the Mentor Graphics’s QuickSim II environment. For relatedinformation, refer to the following Mentor Graphics manuals:●●●Common Simulation User's and Reference ManualGetting Started with QuickSim II Training WorkbookQuickSim II User's Manual134 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsCurrent Support LevelsPlease note the following important items before starting a simulation. SmartModelLibrary models currently:●●●Do support the implementation of location maps. You can use location maps toinstall a library anywhere on the system. Set an environment variable and a locationmap variable before using location maps.Do support extended-time (64-bit) simulations.Do not support the unit delay timing mode.Default Timing ModeThe default timing mode for SWIFT SmartModels is “typ”. You can use thetiming-mode switch at QuickSim invocation time to force the timing mode to be “min”,“typ”, or “max”.Signal Levels and Drive StrengthsSmartModels recognize the nine signal levels and drive strengths listed in Table 16.QuickSim II maps indeterminate strengths to unknowns for “12-state” simulations.The models generate strong and resistive states. The high-impedance unknown state(XZ) is used when a model places an output in the high-impedance state.Table 16: Signal State ValuesSignal LevelDrive Strength Low (0) High (1) Unknown (x)Strong (S) 0S 1S XSResistive (R) 0R 1R XRHigh Impedance (Z) 0Z 1Z XZThe state values shown in bold type are generated by the models. All values arerecognized.October 6, 2003 Synopsys, Inc. 135

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideQuickSim II Command Line SwitchesWhen QuickSim II is invoked from the command line, the following switches are theonly ones recognized by SmartModels.Timing Mode SwitchUse the -timing_mode switch to set the global timing mode to minimum, maximum, ortypical. Unit delay timing mode is not currently supported. Use the following syntaxwhen setting this switch:-timing_mode { min | max | typ }Time Scale SwitchUse the -time_scale switch to adjust time values (delays and checks) to the desiredresolution by specifying the time scale in nanoseconds (ns). The default is 0.1 ns. Usethe following syntax when setting this switch:-time_scale timescaleConstraint Mode SwitchUse the -constraint_mode switch to enable or disable timing constraint checking. Thedefault is “off”. Any value other than “off” causes a model to perform constraintchecking. Use the following syntax when setting this switch:-constraint_mode { off | state_only | messages }136 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsQuickSim II Command InteractionThere are many QuickSim II simulator commands that interact with SmartModels in adesign. Table 17 lists some of the QuickSim II commands that affect SmartModels.Table 17: QuickSim II Command InteractionQuickSim II CommandINITIALIZESIGNAL INSTANCEREPORT OBJECTREREAD MODELFILERESET STATERESTORE STATESAVE STATEWRITE MODELFILEEffect on SmartModelsCauses a model to reevaluate until the simulationreaches DC stability. It will not reset the model orset internal values to the “state_value” specified.Reports the status of selected instances with the“swift_dump” parameter.Not supported by SmartModels. Use the SIGNALINSTANCE command to query a model and reportits status.Reloads any of the configuration files used by amodel, including memory image, JEDEC, MCF,SCF, and PCL command files. Configuration filesare only re-read if the simulation has changed theconfiguration.Causes all models to reinitialize their states to theoriginal time zero (power-up) conditions.Restores all of the model's internal states as part ofthe operation.Records all of the model's internal states as part ofthe operation.Causes a model to “dump” its memory image to afile.SWIFT Command ChannelYou can use the SWIFT command channel to pass commands directly through toSmartModels. Use the QuickSim II SIGNAL INSTANCE command to access thecommand channel.To issue a command for selected instances, use the following:signal instance swift_model -p “command_name [ arguments ]”October 6, 2003 Synopsys, Inc. 137

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTo issue a command for a session, use the following:signal instance swift_session -p “command_name [ arguments ]”For more information on using the SWIFT command channel, refer to “The SWIFTCommand Channel” on page 21.Checking the Model's StatusUse the QuickSim II SIGNAL INSTANCE command to query a model directly. Selectone or more instances in the design and then issue the command to display the internalelement status of all selected instances, as shown in the example below.signal instance swift_dump'/I$1': ' ''/I$1': 'Note: ''/I$1': ' Model template: pal20r4i''/I$1': ' Version: not available''/I$1': ' InstanceName: /I$2742''/I$1': ' TimingVersion: MMI_20R4A-COM''/I$1': ' DelayRange: TYP''/I$1': ' JEDECFile: /user/bobb/design/schematic/selack.jedec''/I$1': ' Timing Constraints: Off''/I$1': ' SmartModel Instance /I$2742(U103:MMI_20R4A-COM), sheet1of schematic at time 0.00 nsec''/I$1': ' ''/I$1': 'Note: SmartModel Windows Description:''/I$1': ' Q20 “PAL Internal Register connected to pin 20”''/I$1': ' Q19 “PAL Internal Register connected to pin 19”''/I$1': ' Q18 “PAL Internal Register connected to pin 18”''/I$1': ' Q17 “PAL Internal Register connected to pin 17”''/I$1': ' SmartModel Windows not enabled for this model.''/I$1': ' SmartModel Instance /I$2742(U103:MMI_20R4A-COM), sheet1of testbed/schematic at time 0.00 nsec''/I$1': ' ''Reconfiguring Models for SimulationYou can use QuickSim II to reconfigure models for additional simulations by:●●●Editing propertiesChanging timing modes of model instancesEnabling or disabling constraint checking138 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsEditing PropertiesAdding or changing the value of a JEDECFile, SCFFile, PCLFile, or MemoryFileproperty causes the simulator to read the file and initialize the model to the power-upstate. Select the following menu choices to change a property:Edit > Properties > Add, Edit > Properties > Change, and Edit > PropertiesChanging Timing ModesSmartModels support minimum, typical, and maximum timing modes. Unit-delay modeis not supported. Select the following menu choices to display the form for changing thetiming mode of specific model instances:Setup > Kernel > Change > Timing ModeYou can also use instance names to specify which instance to change.Constraint CheckingSelect the following menu choices to enable/disable the various timing constraint checks(for example, setup, hold):Setup > Kernel > Constraint Mode > ChangeTo enable constraint checking, select either “State Only” or “Messages” on the ChangeConstraint Mode form. To disable constraint checking, select “Off” on the ChangeConstraint Mode form.SmartModel Library Message FormatsSmartModels issue four different kinds of messages to provide relevant information tousers during simulations. These include:●●●●Error messagesWarning messagesTrace messagesNotesError messages can be generated by timing or usage checks. Warning messages, errormessages, and notes can all be generated by usage checks, depending on the situation.Hardware verification models also issue trace messages, if enabled.Error messages itemize selected information. For example, a setup time violation causesan error message that documents:●●Pin namePart (by instance), reference designator, and component nameOctober 6, 2003 Synopsys, Inc. 139

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration Guide●●●●●Sheet nameDesign nameSimulation timeSignals and edges, as appropriateSetup times (as they occurred and as required by vendor data sheet)Here are some sample messages:‘/I$2751':‘ '‘/I$2751':‘? Error: Unknown signal level on CLK pin.'‘/I$2751':‘? This will probably cause problems later in thesimulation.'‘/I$2751': ‘? SmartModel Instance /I$2751(U102:MC68030-20), sheet1 ofschematic at time 0.0'‘/I$2790': ‘ '‘/I$2790': ‘Note: Loading the memory image file “/user/bobb/design/schematic/rom_image.0_7”'‘/I$2790': ‘SmartModel Instance /I$2790(U201:I27512), sheet2 ofschematic at time 0.0'‘/I$2790': ‘ --- 14 values have been initialized.'‘/I$2751': ‘ '‘/I$2751': ‘! Warning: Unknown signal level on DSACK0_PIN.Assuming DSACK0_PIN is 1.'‘/I$2751': ‘! SmartModel Instance /I$2751(U102:MC68030-20), sheet1 ofschematic at time 200.0'‘/I$2751': ‘Trace: Returning read data to PCL program:'‘/I$2751': ‘ [0]=00000BFE, [1]=00000000, [2]=00000000, [3]=00000000'‘/I$2751': ‘ [4]=00000000, [5]=00000000, [6]=00000000, [7]=00000000,[8]=00000000'‘/I$2751': ‘ SmartModel Instance /I$2751(U102:MC68030-20), sheet1 ofschematic at time 1750.0'‘/I$2751': ‘ '‘/I$2751': ‘Trace: PCL Bus Cmd: Read. Control=06, Addr=00000004,Bytes=4.'‘/I$2751': ‘ SmartModel Instance /I$2751(U102:MC68030-20), sheet1 ofschematic at time 1750.0'140 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsUsing SmartModel Windows with QuickSim IISmartModel Windows is a SmartModel Library feature that can be used for moreefficient system-level verification and debugging by allowing you to view windowelements during simulation runs for microprocessor, PLD, memory, and peripheralmodels.Window elements that can be viewed include registers, pointers, states, or latches (forexample), depending on the part being modeled. This section provides informationabout how to interact with SmartModel Windows using QuickSim II. SmartModelWindows can be used to:●●●●●●Review window element values and set breakpointsSingle-step through simulationsChange window element values before proceeding with a simulationTrace instruction executionRename instancesCombine register elementsMost SmartModels contain predefined window elements that correspond to themanufacturer's specifications. To determine if a specific model is equipped withSmartModel Windows, check the model's online datasheet.How SmartModel Windows WorksSmartModel Windows couples the models and the simulator so that model elements canbe used almost as if they were nets in the design. Normal QuickSim II commands areused with SmartModel Windows, except that an instance designator must be added to aQuickSim II command to address a model's window elements (even at the top level).The general format for using QuickSim II commands with SmartModel Windows is:command model_instance/element_nameUse any of the following commands to enable window elements with the simulator:ADD LISTS model_instance/element_nameADD MONITORS model_instance/element_nameADD TRACES model_instance/element_nameWindow elements must be activated with one of the preceding commands in order forSmartModel Windows to begin displaying data. Each model's online datasheet lists itspredefined window elements, which are available during simulation. Using windowsyou can read or display elements, force new values onto them, and stop the simulationbased on their values.October 6, 2003 Synopsys, Inc. 141

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTracing Instruction ExecutionSmartModel Windows provides the ability to trace peripheral component activity in adesign. Most larger peripherals and microprocessors equipped for SmartModelWindows have a 1-bit element named TRACE_ENABLE. Setting TRACE_ENABLE toone (1) causes trace messages to display in the transcript window.Use the following command to enable instruction tracing for a model:FORCE model_instance/TRACE_ENABLE 1Some trace message examples follow:‘I$2752': ‘Trace: Logical Master writing to PMMU Operand Address CIR.‘I$2752': ‘SmartModel Instance /I$2752(U103:MC68851-12), sheet1 ofmy_design at time 819500.0‘I$2752': ‘Trace: MC68851 is starting a table search using CRP.‘I$2752': ‘SmartModel Instance /I$2752(U103:MC68851-12), sheet1 ofmy_design at time 822150.0Setting Breakpoints and Word TriggeringUse the ADD BREAKPOINT command to stop the simulation at critical points andexamine internal window elements. You can set breakpoints based on the contents ofspecific elements inside components within the design. For example, the followingcommand causes the simulation to stop at the breakpoint when the specified condition ismet.ADD BREAKPOINT (model_instance/TC==0B)You can use Boolean expressions with the Add Breakpoint command to set up complexword triggers that provide a logic analyzer during simulation. For example, thefollowing command causes the simulation to stop at the breakpoint when both of the twospecified conditions are met.ADD BREAKPOINT ((model_instance/SCC!=0)&&(model_instance/TC==B))Trigger terms do not have to refer to the same instance or model. In addition, net valuesand window element contents can be combined to make trigger terms.Single-Step SimulationThe ADD BREAKPOINT command defaults to stopping the simulator when a signal orexpression in a window element changes state. As a result, you can use the ADDBREAKPOINT command to single-step through a simulation.142 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsRenaming InstancesUse the ADD SYNONYM command to rename instances with easier-to-remembersubstitute names. For example, to rename a model for an MC68851 with an instancename of “I$289” to an easier-to-remember name such as “PMMU,” use the followingcommand:ADD SYNONYM 'PMMU' I$289Once you add a synonym you can use it in place of the original instance name incommands. For example, the following command lists the MC68851 translation controlregister.ADD LISTS HEX PMMU/TCCombining Register ElementsYou can use the ADD BUS command to combine meaningful 1-bit elements of a PLDinto a single bus that can be viewed or changed after the PLD has been programmed.This saves effort compared to dealing with each 1-bit element one at a time. Table 18shows the elements of a sample device, the Texas Instruments TIBPAL22V10. Allwindow elements for this example are 1-bit wide with read and write access.Table 18: Elements in a TIBPAL22V10 DeviceElementDescriptionQ23 PAL Internal Register connected to pin 23Q22 PAL Internal Register connected to pin 22Q21 PAL Internal Register connected to pin 21Q20 PAL Internal Register connected to pin 20Q19 PAL Internal Register connected to pin 19Q18 PAL Internal Register connected to pin 18Q17 PAL Internal Register connected to pin 17Q16 PAL Internal Register connected to pin 16Q15 PAL Internal Register connected to pin 15Q14 PAL Internal Register connected to pin 14October 6, 2003 Synopsys, Inc. 143

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideNoteBecause the block diagram of this part does not denote specific names forthe elements, their names reflect the output pin numbers on the DIP symbol(for example, pin 23 maps to Q23).For example, to program the first six elements listed in Table 18 as counters and registerthe last four elements as data pins from an I/O port, you would use the followingcommands:ADD BUS CNTR I$230/Q23, I$230/Q22, I$230/Q21, I$230/Q20, I$230/Q19,I$230/Q18ADD BUS DATA I$230/Q17, I$230/Q16, I$230/Q15, I$230/Q14ADD LISTS CNTR DATA -C -HEXChanging Program Flow by Setting ValuesYou can use the SmartModel Windows feature to shorten large repetitive loops. Forexample, if a DMA controller has initiated a DMA transfer of 1,024 words to mainmemory, you can view the transfer of the first couple of words before stopping thesimulation. By artificially setting the value of the DMA's transfer control register, youcan control which part of the transfer to view. You can then view the last few words asthey are transferred without having to wait for the entire process.Be careful when inserting values into window elements, especially when forcing datainto program counters and instruction registers. This SmartModel Windows feature isrecommended only for users who completely understand the implications of what isbeing inserted into an element.When forcing a value onto an element, the FORCE command is always interpreted as ifthe -CHARGED switch were present. This means that the forced value vanishes whenanother event attempts to update the window element. It is not possible to FIX or WIREa forced value on a window element.Custom SymbolsSynopsys provides symbols representing default package pinouts for SmartModels.However, you may need to create custom symbols for some of the following reasons:●●To conform to internal drafting requirementsTo make a symbol match a component's pinout●To match external drafting specifications (for example, military specifications)144 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsUsers who choose to create custom symbols as an alternative to using the symbolsprovided can:●Modify a SmartModel Symbol. Start with the SmartModel symbol and modify itto match your drafting requirements. The value of the user PIN property can now bechanged without corrupting the value of the compiled PIN property.● Create a New Symbol. Create the symbol with your pin values, figure out thecorresponding pin names used by the model, and change the user pin values to thosenames.To create custom symbols, follow these steps:1. Provide required SWIFT properties on the symbol.2. Register the component.3. Map pin names to standard SWIFT pin names.SWIFT PropertiesThe following symbol properties are required to interface with a SWIFT model:● model● TimingVersion●●●pinpintypeswift_templateRefer to Table 13 and Table 14 for information about other required symbol properties.Component RegistrationWhen creating new symbols, you must add the SWIFT model to the componentinterface by “registering” the model with a type of “SWIFT”.For example, suppose you have created a new component called “my_ttl00” and youwant to use the SmartModel Library “ttl00” binary as the simulation model. You wouldregister the ttl00 model as follows:reg_model $MY_DIR/my_comp_lib/my_ttl00 -type SWIFT -label 'my_label'October 6, 2003 Synopsys, Inc. 145

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuidePIN_NAME MappingThe two methods for creating custom symbols described in “Custom Symbols” on page144 cannot be used to map bus symbol pins to model pins. You must use a pin_map fileto accomplish this sort of custom symbol creation, as explained in the followingsections.PIN PropertyA PIN property can have two distinct values in Design Architect, as follows:●●Compiled pin valueUser pin valueThe compiled pin value must be the same value that is used in the model. When initiallyadding a pin to a symbol, both these values are set to the specified value. For example,naming a pin “A” causes both its user pin value and the compiled pin value to be “A”.Changing a PIN property value causes the compiled pin value to track the user pinvalue. Specifically changing the compiled PIN property value disables this trackingmechanism. To re-enable tracking, set the value of the compiled PIN property to null(“”).PIN_NAME PropertySmartModel Library symbols include a property called PIN_NAME that is used purelyfor graphical purposes. The PIN_NAME property is provided because SmartModelLibrary symbols do not completely match the Mentor Graphics requirements for pinnames. Deleting a PIN_NAME property does not affect model functionality in any way.AttentionDo not confuse the PIN property with the PIN_NAME property onSmartModel symbols.Purpose of the pin_map FileUse the pin_map file to map custom symbol pins to model pins. If your symbol does nothave buses, then you can use the “user pin value” and “compiled pin value”combinations previously described to do this mapping without using the pin_map file. Ifyou have bus pins on your symbol, then you need to use a pin_map file and ensure thatthe PKG symbol property is set to the value “BUS”. Following is a general descriptionof the pin_map file which describes both cases.NoteError messages cite the pin names used by the model, not those on thesymbol or in the pin_map file.146 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsHow the pin_map File WorksAt startup, a PKG symbol value of “BUS” triggers the simulator to look for a pin_mapfile for that model. The pin_map cross-reference file is a free-format ASCII file. Itcontains statements that use the following syntax:pin_type symbol_pin [ = ] model_pin_names ; [ # comment_text ]Following are descriptions of the fields and options.pin_typesymbol_pinMust be the same value as the PINTYPE property of themodel. Valid values are IN, OUT, IXO, and IO. Do not changethis value.The new pin name you want to use on your symbol. This is thesymbol's user PIN property, not its PIN_NAME property.= Optional.model_pin_namesA statement can have from 0 to 767 model_pin_names,separated by spaces, tabs, or new lines. The model_pin_namesare ordered from most significant to least significant and referto the PIN property, not the PIN_NAME property.; Ends a statement.# Starts a comment, which runs to the end of the line.October 6, 2003 Synopsys, Inc. 147

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideExample of a pin_map FileThe following example pin_map file customizes the standard symbol supplied with themodel of the National Semiconductor DP8429 DRAM controller shown in Figure 4.Figure 4: National Semiconductor DP8429 DRAM ControllerIn the example pin_map file shown below, the names that are changed on the firstsymbol are labeled CS, RASIN, R/C, CASIN, WIN, RA, RB, RC, RD, and M2. Theywill have an “L” added to the name to denote that they are asserted low. Notice that abus has been defined for each of these sets of pins: Q0 through Q9, R0 through R9, C0through C9, and B0 through B1.## DP8429 PIN NAME CHANGES#IN CSL = CS ;IN RASINL = RASIN ;IN CASINL = CASIN ;IN RCL = R/C ;IN WINL = WIN ;IN RFSH = M2 ;IN R = R9 R8 R7 R6 R5 R4 R3 R2 R1 R0;148 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsIN C = C9 C8 C7 C6 C5 C4 C3 C2 C1 C0;IN B = B1 B0;OUT WEL = WE ;OUT RAL = RAS3 ;OUT RBL = RAS2 ;OUT RCL = RAS1 ;OUT RDL = RAS0 ;OUT Q = Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0;Conditional Pin MappingUse a conditional clause in the pin_map file to cause the model to use different parts ofa pin_map file based on the value of a certain property. The syntax is:% property_name property_valueThis method is used by the models to map the pins from the BUS symbols to the model.The pin map parser searches for the property_name in the design database and thencompares the property_value. If the property is not present, or if the actual value of theproperty does not match the property_value exactly, everything in the file until the nextpercent sign (%) is ignored.The following example shows the pin_map file that provides mapping from the pin tothe bus symbols for the Logic Devices LSH32 32-bit barrel shifter.## Bus Package for the LSH32#% PKG BUSIN I = I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 ;OUT Y = Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ;IN SI = SI4 SI3 SI2 SI1 SI0 ;OUT SO = SO4 SO3 SO2 SO1 SO0October 6, 2003 Synopsys, Inc. 149

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideFigure 5 illustrates both symbol types.Figure 5: Bus and Pin SymbolsNoteThe properties on custom symbols must be the same as those on standardSmartModel symbols.150 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsUsing DesignWare Memory Models withQuickSim IIThis section explains how to use DesignWare Memory Models with QuickSim II.DesignWare Memory Models (DWMMs) are SWIFT-compatible binary simulationmodels, identified by an _mx extension (model_mx.).This section explains how to install and use DWMM models in the Mentor GraphicsDesign Architect (schematic capture) and QuickSim II (simulation) environments:● “Installing the QuickSim II SWIFT Interface for DWMM” on page 151● “DWMM Schematic Capture” on page 151● “DWMM Logic Simulation” on page 158● “DWMM Custom Symbols” on page 163Installing the QuickSim II SWIFT Interface for DWMMThe procedure for installing the QuickSim II interface software for DWMM is the sameas for SmartModels: see “Installing the QuickSim II SWIFT Interface” on page 125.DWMM Schematic CaptureAdding a DWMM to a design schematic involves identifying the desired symbol,instantiating it, and editing its properties as necessary.Synopsys supplies a complete Schematic Editor menu system in the QuickSim IIenvironment that you can use to identify and instantiate a component. You can alsoinstantiate symbols from the command line and edit property values interactively usingDesign Architect. This section provides information about both approaches to building adesign, as well as an introduction to the symbols and their properties.For more information about Design Architect and the Schematic Editor, refer to theMentor Graphics documentation.October 6, 2003 Synopsys, Inc. 151

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideDWMM SymbolsSynopsys provides a pin-based symbol for each DWMM. Each of these symbolsincludes only the pins used for simulating that model.DWMM symbols are not intended to represent actual physical device packages. If yourequire customized, package-specific symbols, you will need to create them yourself:see “DWMM Custom Symbols” on page 163.NoteFor information about symbol compatibility with different versions of theDesign Architect software, see the SmartModel Library Release Notes.DWMM Symbol PropertiesAssigning specific values to symbol properties completes the definition of a DWMMmodel for QuickSim. The properties used on the DWMM symbols provided for theMentor Graphics Design Architect environment include the following:●●●Symbol properties for DWMM parameters (used to configure the model).Symbol properties required for simulation (required to enable simulation underQuickSim II).Optional symbol properties (provided for compatibility with many optionalSmartModel properties).You can edit symbol property values with the Schematic Editor pop-up menu, or byusing the QuickSim II CHANGE TEXT VALUE command.The properties are hidden or visible as controlled by the visibility attributes set by yourlibrary manager. Figure 6 shows the positions of the visible properties on a DWMMsymbol supplied by Synopsys.152 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTimingVersionInstanceName U?PIN_NAMEPINTYPEININaddr_7addr_610Max.1111111115.32’h0-2DelayRangeDefaultDataMemoryFileMessageLevelModelConfigModelAliasINaddr_5ModelIdINaddr_4dq_7IXOINaddr_3dq_6IXOINaddr_2dq_5IXOINaddr_1dq_4IXOINaddr_0dq_3IXOINoe_ndq_2IXOINce_ndq_1IXOINwe_ndq_0IXOFigure 6: DWMM Visible Symbol PropertiesSymbol Properties for DesignWare Memory Model ParametersMost properties on a DWMM symbol are DWMM parameters — model-specific valuesused to configure the model. For details, see Table 5, “DesignWare Memory ModelSWIFT Parameters,” on page 29.Table 19 lists the set of symbol properties of DWMM parameters.Table 19: Symbol Properties for DesignWare Memory Model ParametersPropertyInstanceNameTimingVersionDelayRangeDescriptionProvides an identifier for use in simulation messages.Selects the timing version to use with a model. Anyvalue assigned to the TimingVersion property must bea valid timing version for that model.Sets the model’s timing mode in HDL simulators. Noeffect in QuickSim.October 6, 2003 Synopsys, Inc. 153

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTable 19: Symbol Properties for DesignWare Memory Model ParametersPropertyDefaultDataMemoryFileMessageLevelModelConfigModelAliasModelIdDescriptionSpecifies the data value returned from all uninitializedmemory addresses. On model symbols supplied bySynopsys, the DefaultData value is presented inbinary format.Specifies the file name of a memory image file topreload during model initialization. If MemoryFile isset to either a null string or a single period(MemoryFile = “.”), memory image preloading duringinitialization is disabled.You can use an absolute or a relative path to point to afile. If you use a relative path, it is resolved relative tothe value of $MGC_WD.Represents a 32-bit control word, and controls themodel’s messages. The lowest five bits enable anddisable the following message types:bit 0 — Error messagesbit 1 — Warning messagesbit 2 — Timing messagesbit 3 — X handling messagesbit 4 — Info messageTo enable a message type, set the corresponding bit to1; to disable, set the bit to 0.Represents a 32-bit control word, and used by somemodels to configure aspects of operation (for example,the optional power-on sequence in SDRAM models).Refer to your model’s datasheet for information aboutusing the ModelConfig value with your model.Model-specific identifier for testbench commands inHDL simulators. No effect in QuickSim.Model-specific identifier for testbench commands inHDL simulators. No effect in QuickSim.154 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsSymbol Properties Required for DesignWare Memory Model SimulationTable 20 lists the symbol properties required for simulation.Table 20: Symbol Properties Required for DesignWare Memory ModelSimulationPropertyMODELPINPINTYPEDescriptionContains a label registered as type “SWIFT”.Logic simulation requires each pin on a symbol tohave a property. A PIN property has two associatedvalues:● User pin name● Compiled pin nameYou can change the user pin name to adhere todrafting standards, but you must not change thecompiled pin name.Each model pin has an associated PINTYPEproperty that describes the pin type: IN, OUT, IXO,or IO. This property is required by QuickSim II andcannot be changed.SWIFT_TEMPLATE Specifies the model name, and cannot be changed.October 6, 2003 Synopsys, Inc. 155

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideOptional DesignWare Memory Model Symbol PropertiesTable 21 lists optional symbol properties.Table 21: Optional DWMM Symbol PropertiesPropertyCOMPPIN_NAMEREFDescriptionProvides an interface to layout or otherapplications. Synopsys does not use this property.The visible text on a symbol representing a pin’sname. This text has no effect on the model’soperation.Provides an identifier for use in simulationmessages. REF is assigned the default value“InstanceName” with the property attribute“expression”. This causes the REF property to trackthe value of the InstanceName property forSynopsys symbols.Building a Design Using the MenusDWMM models use the same Design Architect menu system as SmartModels.To add DWMMs to a design using the menu system, follow these steps:1. Use the Schematic Editor menu system to move through the menus and identify themodel.2. Instantiate the model’s symbol on the schematic sheet.3. Use Design Architect or the Schematic Editor to edit property values if needed.Menu Information for DWMMThe following lists SmartModel menu levels and items as they apply to DWMM,starting from the top menu level. (The top menu level corresponds to the menu accessedby choosing Libraries from the Design Architect menu bar).●Top levelDWMM models are listed under Logic Modeling SmartModel Library.●FunctionDWMM models are listed under Memories.●SubfunctionThe Memories menu lists basic memory types: FLASH, SDRAM, SRAM, etc.156 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models●VendorEach subfunction menu item has an associated vendor menu that lists the partmanufacturers for that group of models.●PartEach vendor menu item has an associated part menu that lists all available DWMMmodels and SmartModels.●ComponentEach part menu items has an associated component menu that lists the timing and/orsymbol versions for a particular model.ExampleThe following sequence of menu selections would select timing version “10” of theDWMM model of the Cypress cy7c199:SmartModel Library > Memories > SRAM > CYPRESS > CY7C199-10 > 10Building a Design Without the MenusIf you are familiar with the SmartModel Library, you may prefer to use SchematicEditor commands to build designs. This can be faster than using the menu system.The basic steps are essentially the same:1. Identify the model you need.2. Instantiate the model’s symbol on the schematic sheet.3. Use Design Architect or the Schematic Editor to edit property values if needed.Creating An InstanceUse the $add_instance command to instantiate a part in the Schematic Editor, as shownin the following minimal command:$add_instance ("$LMC_HOME/special/qsim/symbols/model_name")You can also include the DWMM symbol properties on the same line, as in theseexamples (all punctuation marks are required):●Example of defining a single property:$add_instance ("$LMC_HOME/special/qsim/symbols/model_name",,,,["property_name","property_value"])October 6, 2003 Synopsys, Inc. 157

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration Guide●Example of defining multiple properties:$add_instance ("$LMC_HOME/special/qsim/symbols/model_name",,,,["property_name_1","property_value_1","property_name_2","property_value_2","property_value_3","property_value_3"])If a property value is not specified, its default value is selected.DWMM Logic SimulationThe following sections discuss the use of DWMMs for logic simulation in the MentorGraphics QuickSim II environment. For more information, see the following MentorGraphics manuals:●●●Common Simulation User’s and Reference ManualGetting Started with QuickSim II Training WorkbookQuickSim II User’s ManualCurrent Support LevelsBe sure to keep the following in mind before starting a simulation:●●●DWMM models support the implementation of location maps. You can use thesemaps to install a library anywhere on the system. Set an environment variable and alocation map variable before using location maps.DWMM models support extended-time (64-bit) simulations.DWMM models do not directly support unit-delay timing mode via QuickSim’stiming mode command line or interactive setting. However, you can run a DWMMmodel in unit-delay mode by setting its TimingVersion property to “none”.Default Timing ModeThe default timing mode for DWMM models is “typ”. You can also use thetiming-mode switch when invoking QuickSim to force the timing mode to “min”, “typ”,or “max”.Signal Levels and Drive StrengthsDWMM models recognize the nine signal levels and drive strengths listed in Table 22.QuickSim II maps indeterminate strengths to unknowns for “12-state” simulations.The models generate strong and resistive states. The high-impedance unknown state(XZ) is used when a model places an output in the high-impedance state.158 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsThe state values shown in bold are generated by the models. All values are recognized.Table 22: DWMM Signal State ValuesSignal LevelDrive Strength Low (0) High (1) Unknown (x)Strong (S) 0S 1S XSResistive (R) 0R 1R XRHigh Impedance (Z) 0Z 1Z XZQuickSim II Command Line SwitchesWhen QuickSim II is invoked from the command line, DWMM models recognize onlytwo switches: -timing_mode and -time_scale.●-timing_mode: use this switch to set the global timing mode to “min”, “max”, or“typ”:-timing_mode { min | max | typ }●The default = typ, except if the model’s TimingVersion property is set to none, inwhich case the model runs in unit-delay mode.-time_scale: use this switch to adjust the resolution of time values (delays andchecks) by specifying the time scale in nanoseconds (default = 0.1 ns):-time_scale timescaleWarningDWMM models must use a timescale value of 0.1 or less. Values greaterthan 0.1 cause DWMM models to crash.October 6, 2003 Synopsys, Inc. 159

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideUnsupported QuickSim II CommandsTable 23 lists several common QuickSim II simulation commands that are not supportedby DWMM models, and the effects these commands have if used with DWMM models.Table 23: Common Unsupported QuickSim II CommandsQuickSim II CommandREREAD MODELFILERESTORE STATESAVE STATEWRITE MODELFILEEffect on DWMMDoes not cause a DWMM model to reload itsmemory image file. If this command is issuedanytime after time 0, the DWMM model may notsimulate correctly.Attempting to restore the saved state of a DWMMmodel crashes the model, and subsequently thesimulation.Not harmful, but the resulting saved state cannot beused to restore the simulation state since RESTORESTATE is fatal.Not harmful, but does not cause a DWMM model tosave a memory image file.SWIFT Command ChannelDWMM models are not designed to use the SWIFT command channel. Nevertheless,the models support the following two commands, both of which are issued using theQuickSim II command SIGNAL INSTANCE.●●ReportStatus — prints a message that describes the configuration status of a model.To issue ReportStatus for selected instances:$signal_instances("swift_model", "ReportStatus", "model_name");Trace ON | OFF — when enabled (“ON”), traces the SWIFT simulation session, andcreates an “lmc_trace.out” file.To enable tracing for selected instances:$signal_instances("swift_session", "Trace on", "model_name");For more information on using the SWIFT command channel, see “The SWIFTCommand Channel” on page 21.160 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsChecking the Model’s StatusTo check the status of a DWMM model, use the QuickSim II SIGNAL INSTANCEcommand to query the model directly. For example:$signal_instances("swift_model", "ReportStatus", "/$I1");’/I$1’: ’ ’’/I$1’: ’Note: ’’/I$1’: ’ Model Logical Name: ssram08x1k_mx’’/I$1’: ’ Model Physical Name: ssram08x1k_mx’’/I$1’: ’ Model ’.mdl’ Version: 01004’’/I$1’: ’ Model Directory: /d/tools/lmc_home/models/ssram08x1k_mx’’/I$1’: ’ Model ’.lmc’ Name: /d/tools/lmc_home/data/solaris.lmc’’/I$1’: ’ Model-reported Version of Main Shared Library: 01001’’/I$1’: ’ Model-reported Version of SmartLink Interface: v1.0’’/I$1’: ’ InstanceName: /I$1’’/I$1’: ’ DefaultData: 00000000’’/I$1’: ’ DelayRange: TYP’’/I$1’: ’ MemoryFile: U1_memory_image’’/I$1’: ’ MessageLevel: 15’’/I$1’: ’ ModelAlias: .’’/I$1’: ’ ModelConfig: 32’h0’’/I$1’: ’ ModelId: -2’’/I$1’: ’ TimingVersion: 10’’/I$1’: ’ ModelMapVersion: 01002’’/I$1’: ’ Timing Constraints: Off’’/I$1’: ’ Max Simulation Time Unit: 10**(-10) seconds’’/I$1’: ’ SmartModel Instance /I$1(U1:10), sheet1 ofschematic at time 3600.00 nsec’You can also use the QuickSim menu to request a report on selected or specified objects.For example, the following command would issue a status report for each selectedinstance in the design:QuickSim > Report > Object > SelectedReconfiguring Models for SimulationYou can use QuickSim II to reconfigure models for additional simulations by doing thefollowing:●●●Editing propertiesChanging timing modes of model instancesEnabling or disabling constraint checkingOctober 6, 2003 Synopsys, Inc. 161

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideEditing PropertiesAdding or changing the value of any DWMM model property causes the simulator toreevaluate that property and initialize the model to its power-up state.Use the following menu selections to change a property:●●●Edit > Properties > AddEdit > Properties > ChangeEdit > PropertiesChanging Timing ModesDWMM models support minimum, typical, and maximum timing modes. Use thefollowing menu selection to change the timing mode of specific model instances:Setup > Kernel > Change > Timing ModeUnit-delay mode is supported through the model’s TimingVersion property (though notthrough the timing mode value). To enable a DWMM model to run in unit-delay mode,change the model’s TimingVersion property value to “none”.Constraint CheckingDWMM models use the MessageLevel property to enable or disable timing constraintchecking (such as setup and hold):● To enable constraint checking, set bit 2 of the MessageLevel property value to 1.● To disable constraint checking, set bit 2 to 0.162 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsDWMM Custom SymbolsSynopsys provides symbols representing a simple pin interface for DWMMs. However,in some situations you may need to create custom symbols:●●●To conform to internal drafting requirements.To match external drafting specifications (for example, military specifications).To make a symbol match a component’s pinout.To create custom symbols, you can do the following:● Modify a standard DWMM symbol. Start with the DWMM symbol and modify itto match your drafting requirements. The value of the user PIN property can now bechanged without corrupting the value of the compiled PIN property.● Create a new symbol. Create a symbol with your pin values, find thecorresponding pin names used by the model, and change the user pin values to thosenames.To create a custom symbol for a DWMM model, use the procedure outlined forSmartModels: see “Custom Symbols” on page 144.Required DWMM Symbol PropertiesThe following symbol properties are required to interface with a DWMM model:●●●●modelpinpintypeswift_templateRefer to Table 20 for information about the required symbol properties. In addition, seeTable 19 and Table 21 for information about DWMM model configuration propertiesand optional model properties.October 6, 2003 Synopsys, Inc. 163

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideUsing Hardware Models with QuickSim IIThis section describes how to configure Release 3.5a of ModelAccess for QuickSim II.ModelAccess is the software you use to interface hardware models with the simulator.Before you begin, review the release notes for ModelAccess for QuickSim in theHardware Modeling Release Notes. If you are using the C-series releases of QuickSimII, you must use R3.0 or better of the ModelAccess for QuickSim II interface software.These instructions assume that you have already installed the following software:●●Mentor Graphics software, including QuickSim II V8.6 or later; and the DesignData Port package, as described by Mentor Graphics Corporation.R3.1a or later of ModelSource or LM-family hardware modeling software.Setting up Hardware Models in QuickSim IITo set up the LM-family ModelAccess interface software for QuickSim II, complete thefollowing steps:1. “Running lmc_hm_install” on page 1642. “Rebuilding the Mentor Graphics Tree” on page 166Running lmc_hm_installTo run the ModelAccess installation script, enter the following commands.% cd install_dir/sms/maqs_30/lmc_hm.$vco/bin% lmc_hm_install -m mgc_home -l lm_home -p ma_homewhere:●●●●$vco is the vendor CPU operating system suffix that corresponds to your platform,as shown in Table 24.mgc_home is the directory path that contains the Mentor Graphics software tree.You can use $MGC_HOME if you have set it, or a pathname such as/home/mentor.lm_home is the directory path that contains the LM-family and ModelSource systemsoftware; for example, /home/lm.ma_home is the directory path that contains the ModelAccess interface software; forexample, /home/lmc_hm.sss.164 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTable 24: Mentor Graphics Vendor CPU Operating System SuffixesHostSun SPARC (Solaris)HP 9000 Series 700Vendor CPUOperating System Suffix ($vco)ss5hpuWhen the script completes, the following message appears on the screen:1. Invoke the Mentor Installation tool> cd /an_idea_tree/install8> install2. From the "Mentor Graphics Install" tool window> Admin> Rebuild MGC Tree3. In the "Prompt" window enter the proper path to theMGC_HOME to be rebuilt. Click on> OK4. "Rebuild MGC Tree Results" window appears. AFTER Rebuildcompletes. Click on> OK5. From the "Mentor Graphics Install" tool window> File> Exit6. "Install Warning" window appears. Click on> OKNoteThis process rebuilds the Mentor tree with the newly installed hardwaremodeler package.October 6, 2003 Synopsys, Inc. 165

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideRebuilding the Mentor Graphics TreeThe final step is to rebuild the Mentor Graphics tree using the Mentor Graphicsinstallation script.Using install, version C.11. To invoke this program, enter the following:% cd mgc_home/install8 ./install2. When the install tool appears, use the mouse to select the Admin > Rebuild MGCTree pull-down menu item. The program prompts you to enter the MGC treepathname.3. If you have defined $MGC_HOME, that path will appear; otherwise, enter the fullpathname of the Mentor Graphics tree that you want to rebuild, such as themgc_home pathname described in “Rebuilding the Mentor Graphics Tree” onpage 166.4. Click on OK or press the Return key to accept this pathname. The install programtakes several minutes to rebuild the Mentor Graphics tree. The program prints anumber of messages to the Results screen. You should ensure that no errors orwarnings are printed, especially warnings generated by the lmc_hm packageindicating that you are missing certain Mentor Graphics software packages.5. When the rebuild is complete, click on OK to delete the Results screen.6. Use the mouse to select the File > Exit pull-down menu item.This completes the ModelAccess installation procedure. You are now ready to beginmodel registration and simulation.Using Hardware Models in QuickSim IIThis section describes how to prepare and use hardware models in QuickSim II. Webegin with an overview of the Mentor Graphics design environment that describes whymodels must be registered in order to function in this environment. The section alsodescribes how to use the lm_model utility to register hardware models.The operation of the hardware modeling system during simulation is transparent to theuser in most respects. However, a number of signal instance commands are available toenable or disable QuickSim II or hardware modeling features for selected instancesduring simulation. This section provides descriptions and examples of those commands.166 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsThe Mentor Graphics Design EnvironmentIn the post-V8.0 QuickSim-family environment, an instance of a component placed on aschematic references a component interface. A component interface contains a set ofdescriptors that define aspects of a component, such as its functionality, graphicalrepresentation (symbol), and timing constraints.There can be several variations of each descriptor for a component, such as:●●●Several functional descriptions of the component using different modeling methodssuch as BLM, VHDL, or hardware models.Several graphical descriptions (symbols) of the component such as ANSI,MG_STD, or your company standard.Several technology descriptions (timing constraints) of the component withdifferent timing grades.The Mentor Graphics analysis tools use the value of the MODEL property as a label toidentify the descriptors that define the model. For example, Figure 7 shows an instancewith a MODEL property of $lm. The $lm label is the default label for the functionaldescription of a hardware model. By examining the model table of the componentinterface, a match can be found between the MODEL property and the files thatcomprise the functional description of the hardware model.October 6, 2003 Synopsys, Inc. 167

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideMentor Graphics SchematicASIC1InstanceMODEL= $lmComponentInterface$lmdefault_symdef_techFunctional DescriptionASIC1.rss_1ASIC1.mgc_lm.attrGraphical DescriptionASIC1.smbl_1ASIC1.mgc_symbol.attrTechnology Descriptiontechnology.tstechnology.tecf_1technology.Tf_tfile_do.attrFigure 7: Sample Component Interface for a Hardware ModelMentor Graphics analysis tools use the following rules to determine the appropriatedescriptors:1. If a label match is found, the analysis tool uses the descriptor identified by the label.2. If a label match is not found, the analysis tool uses the default label for thedescriptor.3. If a label match is not found and there is no default label, the descriptor is optionaland is not used.168 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsModel RegistrationBecause multiple descriptions can exist for the same component, you must register eachmodel to specify the model’s component interface and descriptors. The lm_model utilityis a tool for registering hardware models. If a QuickSim II component does not alreadyexist, lm_model creates one, along with a component interface that specifies thefunctional, graphical, and technology descriptions for the model.The lm_model utility registers a hardware model in three steps, using the model’s ShellSoftware as source files:1. Creates a symbol for the model and registers it with the component interface.2. Creates, compiles, and registers a technology File, which contains the timingdescription of the model in a Mentor Graphics proprietary format. The user canchoose to use either this technology file or the Shell Software timing files duringsimulation. For more information, refer to “Timing Shell Selection” on page 179.3. Registers the functional description with the component interface.The lm_model command, as illustrated in Figure 8, calls a number of other utilities. Thereg_model utility and Technology Compiler (tc) are Mentor Graphics utilities; for moreinformation about these utilities, refer to your Mentor Graphics documentation. Formore information on the tmg_to_ts converter, refer to “lm_model Command Reference”on page 185. For more information on the lm_model utility, refer to “tmg_to_tsCommand Reference” on page 188.October 6, 2003 Synopsys, Inc. 169

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideShell SoftwareASIC1.MDLASIC1.DEV ASIC1.DCLPGA.PKG ASIC1.TCKPGA160.ADP ASIC1.TRKASIC1.OPT ASIC1.DLYASIC1.NAM ASIC1.FRCreg_modellm_modeltmg_to_tstechnology.tsTechnologyCompiler(tc)FunctionalDescriptionASIC1.mgc_lm.attrASIC1.rss_1GraphicalDescriptionASIC1.mgc_symbol.attrASIC1.smbl_1TechnologyDescriptiontechnology.tecf_1technology.Tf_tfile_do.attrFigure 8: Hardware Model Registration170 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsRegistering a Model with lm_modelAll hardware models, whether user-created or purchased from Synopsys, must beregistered with the lm_model utility before you can use them in the QuickSim IIsimulation environment. The following list shows the basic steps involved in preparinga hardware model for simulation:1. Running the lm_model Utility, discussed next.2. Checking the Transcript for any errors or warnings.3. Editing the Symbol to meet any additional symbol conventions (optional).4. Verifying the Technology File(not required if Shell Software timing files are used inplace of this file; for more information, refer to “Timing Shell Selection” onpage 179).Running the lm_model UtilityYou can use the lm_model shell command to register a hardware model. To runlm_model, use the following syntax.Syntaxlm_model input_dir [output_path] [-Dir name] [-LAbel label][-Mdl mdl_filename] [-Step Register|Symbol|Timing|Update] [-Replace]For a complete description of lm_model syntax and options, refer to “lm_modelCommand Reference” on page 185.ExampleThe following example shows how you might register a 74LS74 model which has amodel file named 74LS74A.MDL. This example assumes that $MGC_WD is set to/user/models, which contains a Shell Software directory called 74ls74.lm_model 74ls74 -m 74LS74AThis command creates a /user/models/74LS74 component directory—if one did notalready exist—containing the files shown in Table 25.Table 25: Sample Component DirectoryFile74LS74A.rss_174LS74A.mgc_lm.attrpart.part_1DescriptionRegistered Shell SoftwareCompiled and registered Shell SoftwareEDDM partOctober 6, 2003 Synopsys, Inc. 171

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTable 25: Sample Component Directory (Continued)FileDescriptionpart.Eddm_part.attr74LS74.smbl_174LS74.mgc_symbol.attr74LS74A_tech.ts74LS74A_tech.tecf_174LS74A_tech.Tf_tfile_do.attrEDDM partSymbol graphicsSymbol graphicsSource technology fileCompiled technology fileVersioned technology fileNotePrevious versions of lm_model copied Shell Software source files into thecomponent directory and registered these files. However, the current versionregisters only a reference pathname to the Shell Software files and does notcopy the files.Checking the TranscriptThe transcript displays information about the progress of the registration, in addition tonotes, warnings, and errors.The lm_model utility checks that the Shell Software is syntactically and semanticallycorrect; this is equivalent to running the lm Check Shell Software utility. If lm_modelencounters an error condition, it stops execution and prints a message describing thesource of the error. Warning and information messages print to the screen, but do nothalt the execution of lm_model.If you get an error, you should fix the problem in the Shell Software and then runlm_model again to complete the registration.The following is an lm_model transcript for the 74LS74 model:// ModelAccess for QuickSim II v2.0, (a.k.a. lmc_hm v2.0)// lm_model v8.5_2.1 Fri Oct 18 18:32:32 PDT 1996// Note: Input directory "74ls74"// resolves to "/user/johnd/lmc/qa/lmc_hm/work.sss/74ls74".// Note: Output directory "74LS74"// resolves to "/user/johnd/lmc/qa/lmc_hm/work.sss/74LS74".//// Note: Using "74LS74A.MDL" file for conversion.// Note: Compiling symbol generator program.// Note: Linking symbol generator program.// Note: Creating symbol.172 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models// tmg_to_ts v8.5_2.1 Sat Oct 19 20:18:24 PDT 1996// Falcon Framework v8.5_2.5 Thu May 30 17:31:43 PDT 1996//// Copyright (c) Mentor Graphics Corporation, 1982-1995, All Rights Reserved.// UNPUBLISHED, LICENSED SOFTWARE.// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.//// Mentor Graphics software executing under Sun SPARC SunOS.//// TC - The Technology Compiler v8.5_2.2 Sat Jun 22 10:56:50 PDT 1996// Falcon Framework v8.5_2.5 Thu May 30 17:31:43 PDT 1996//// Copyright (c) Mentor Graphics Corporation, 1982-1995, All Rights Reserved.// UNPUBLISHED, LICENSED SOFTWARE.// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.//// Mentor Graphics software executing under Sun SPARC SunOS.////// Note: lm_model completed successfullyEditing the SymbolDuring registration, the lm_model utility reads the Shell Software to determine thedevice’s input, output, and I/O pin names. The utility then flattens all buses to individualbits and generates a Mentor Graphics Design Architect script that creates the symbol.The process uses the following rules to create the symbol:● All input pins are placed starting in the lower left corner and proceeding upwards.●●●●All output pins are placed starting in the lower right corner and proceeding upwards.I/O pins are placed for minimizing the symbol’s height.All buses are grouped with the least significant bit placed lower on the symbol thanthe most significant bit.A single grid spacing is left between buses, grouped scalar pins, input and I/O pins,and output and I/O pins.Since symbol standards vary, you may need to use the Symbol Editor in DesignArchitect to modify the appearance of the automatically-generated symbol. For moreinformation, refer to your Design Architect documentation.October 6, 2003 Synopsys, Inc. 173

.Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideVerifying the Technology FileDuring registration, lm_model calls the tmg_to_ts converter. This converter extractstiming information from the following Shell Software files to create a Technology File:●●●●Variable declarations (.DCL) fileTiming checks (.TCK) fileState tracking (.TRK) fileDelays (.DLY) file● Force values (.FRC) fileThe technology file specifies propagation delays and some timing checks, as well astechnology-dependent data for the simulation model. Table 26 shows how ShellSoftware timing statements are converted into technology file statements.NoteMany Shell Software statements have no technology file equivalents. Thetmg_to_ts converter includes each “untranslatable” statement in thetechnology file as a comment and/or generates a warning message. For thisreason, we recommend that you use the Shell Software timing files insteadof the technology file during simulation. For instructions, refer to “TimingShell Selection” on page 179.Table 26: Shell Software to Technology File ConversionShell Software Statementscycle_time input_state (storage_pin) =timing_specTechnology File StatementsfMIN = min_freq on storage_pin (input_trans)fMAX = max_freq on storage_pin (input_trans)decrement name —default_delay timing_specdelay from input_state (eval_storage_pin) tooutput_state (output_pin) = timing_spectP = timing_spec on eval_storage_pin(input_trans) to output_pin (output_trans)tP = timing_spec on eval_storage_pin(input_trans) to output_pin (output_trans)force_value output_pin = pin_value —hold after input_state 1 (storage_pin) ofinput_state 2 (input_pin) = timing_spectH = timing_spec on input_pin (input_state 2 ) tostorage_pin (input_trans 1 )174 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTable 26: Shell Software to Technology File Conversion (Continued)Shell Software StatementsTechnology File Statementsif (condition) {statements}else_if (condition) {statements}else {statements}end_if—increment name —print (severity, arguments) —pulse_width input_state (storage_pin) = timing_specrecovery after (condition)during (condition)before input_state(storage_pin) =timing_specelse_during (condition)before input_state(storage_pin) =timing_specelsebefore input_state(storage_pin) =timing_specend_duringtW = timing_spec on storage_pin (input_state)No equivalent to maximum pulse width time.—set name = value —setup before input_state 1 (storage_pin) ofinput_state 2 (input_pin) = timing_specstable valid (input_pin) while (store_pin =input_state)tS = timing_spec on input_pin (input_state 2 ) tostorage_pin (input_trans 1 )tSTAB = 0 : 0 on input_pin (V) to store_pin (trans1,trans2)var enumerated_list name = identifier —var counter name = number —when (condition) {statements}else_when (condition) {statements}else {statements}end_whenwith conditionNo equivalents to else_when and else clausesOctober 6, 2003 Synopsys, Inc. 175

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideModifying a Hardware ModelWhenever you change a hardware model’s Shell Software, you need to rerun lm_model.However, you may be able to use the -Step option to perform just the steps you need.The following list provides some guidelines about how to take advantage of the -Stepoption:●●●●●If you change, add, or delete a pin name in the Shell Software, then you must rerunall three steps of lm_model (the default). Because you are recreating the symbol,you must also use the -Replace option. For example:lm_model 74ls74 -rIf you change, add, or delete a timing specification in the Shell Software timing filesand you are using the Technology File in QuickSim II, you should use lm_modelwith the -Step Timing switch. For example:lm_model 74ls74 -s tThis step is equivalent to running tmg_to_ts to create the technology file and thenrunning tc to compile and register it with the component interface.If you make any changes to the Shell Software other than changing pin names andtiming information, you should use lm_model with the -Step Register switch; forexample:lm_model 74ls74 -s rThis step is equivalent to running reg_model.If you have not changed any pin names and want to run both the registration andtiming steps, you can use lm_model with the -Step Update switch to update thecomponent interface without recreating the symbol. For example:lm_model 74ls74 -s uThis switch is particularly useful, because symbol generation is the most timeconsumingstep of registration and you lose all manual edits you have made to asymbol when you regenerate it.If you already have a working symbol, you can use -Step Update to register thehardware model functionality with the existing component. For example, you woulduse -Step Update if you have a different type of model for the same component. Youcan then change the MODEL property in the schematic in order to specify whetheryou want to use the hardware model or another type of model for an instance.176 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsSimulating with Hardware Models in QuickSim IIOnce you have registered each hardware model in your design and set the MODELproperty to the appropriate label for instances that reference those models, you are readyto simulate. You can use the SIGnal INSTance command to turn on and off a number ofQuickSim II or hardware modeling features for selected instances during simulation.Signal Instance Command SummaryTable 27 provides a summary of these features and the specific commands used toimplement them; the subsections that follow describe the features in more depth. Somefeatures can also be implemented through Shell Software statements or the lm utilities;for details, refer to the Shell Software Reference Manual. For instructions on how toselect one or more instances, refer to your QuickSim II documentation.NoteIf the simulator is reset with the $reset_state function, any prior SignalInstance commands are lost because the simulator is reset to the same state itwas at invocation.Table 27: Signal Instance Command SummaryFeature Command DescriptionModel evaluation enable Enables evaluation of the instance byQuickSim II (default)Timing shellselectiondisablelst [-p all]nolst [-p all]Disables evaluation of the instance byQuickSim IISelects hardware model Shell Software files todescribe the instance’s timingSelects the Technology File to describe theinstance’s timing (Default)October 6, 2003 Synopsys, Inc. 177

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTable 27: Signal Instance Command Summary (Continued)Feature Command DescriptionUnknownhandling andpropagationIndeterminatestrength mappingTest vectorloggingTimingmeasurementxp [-p pin_name]x0 [-p pin_name]x1 [-p pin_name]xz [-p pin_name]propagatenopropagatedefault_ propagation-p numberrandom_seed-p seedisizlogvectors-p filenamenologvectorstm [-p filename]notmMaps an unknown input state to the previousstate (Default)Maps an unknown input state to a logic zerostateMaps an unknown input state to a logic onestateMaps an unknown input state to a float statePropagates unknowns through the hardwaremodelTurns off unknown propagation (default)Sets the number of additional sequences to beplayed to the instance when unknownpropagation is enabled (default = 0)Sets the value of the seed for the randomsequence generator when unknown propagationis enabled (default = 0)Maps an indeterminate strength (i) to a strongstrength (s) (default)Maps an indeterminate strength (i) to a highimpedancestrength (z)Turns on test vector loggingTurns off test vector logging (default)Turns on timing measurement: returns theactual measured delays to QuickSim IITurns off timing measurement: uses the delayvalues specified in the Shell Software or in thetechnology file (default)Loop mode loop Turns on loop mode: the modeling systemrepeatedly plays a pattern history to thephysical devicenoloopTurns off loop mode (default)178 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsTable 27: Signal Instance Command Summary (Continued)Feature Command DescriptionInformation dump Reports all available information about theselected instance of a hardware modeled devicelmc[-p shell | allshell]vectorReports the type of timing shell (Shell Softwareor technology file) for the selected instanceReports the runtime vector count of the selectedinstanceModel EvaluationBy default, all component instances are evaluated in QuickSim II. If you want to disableevaluation of models for selected instances, you can use the SIGnal INSTance disablecommand. This command isolates sections of the design and shortens the simulationtime for debugging purposes. To turn model evaluation on again for selected instances,you can use SIGnal INSTance enable.Timing Shell SelectionThe SIGnal INSTance lst command lets you use the hardware model’s Shell Softwaretiming files instead of the default technology file during evaluation of the selectedinstances. You can use the SIGnal INSTance nolst command to switch back to thetechnology file for selected instances.The optional -p all argument enables you to choose the type of timing shell for allhardware models in the design, if you have at least one instance selected. For example,you could use the following command before simulating:sig inst lst -p allQuickSim II ignores the technology files for all hardware models in the design and takethe timing (delays and timing checks) directly from the Shell Software. If you decidedyou wanted to use the technology files instead for all hardware models, you could usethe following command to switch back to the default timing shell without having toselect every instance:sig inst nolst -p allOctober 6, 2003 Synopsys, Inc. 179

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTo select Shell Software timing every time you invoke QuickSim II with a particulardesign, you can create or edit a quicksim.startup file under the design viewpoint. Addthe following line to the file to directly call the function that implements this SignalInstance command:$signal_instances("lst", "all", "/I$1");Substitute the instance name of any hardware modeled device for /I$1.You can also use the actual measured delays from the device as an alternative timingoption with hardware models. For more information about this feature, refer to “TimingMeasurement” on page 182.Performance MonitoringYou can monitor the performance of the hardware modeler and append the results to thesimulator log file after simulation. To enable performance monitoring, in the windowwhere you are running the simulator, enter the following:% setenv LM_OPTION “monitor_performance”For more information, refer to “Performance Monitoring” in the ModelSource User’sManual.Unknown Handling and PropagationThe unknown handling and propagation commands enable you to modify the hardwaremodeling system’s default handling of device input and I/O pins that the simulator setsto unknown.Unknown MappingSince the hardware modeling system cannot present an unknown logic level to aphysical device, unknown values presented to inputs of hardware models must bemapped to known values. The SIGnal INSTance xp, x0, x1, and xz commands mapunknowns for all instances of the selected components to the previous state, logic zero,logic one, or high-impedance (float), respectively. By default, unknowns are mapped tothe previous state. Unknowns mapped to high-impedance are also mapped to theprevious state.You can customize unknown handling per pin by using the -p pin_name argument. Forexample, you can issue the following:sig inst x0sig inst x1 -p clk1These commands map all unknowns for the selected components—except for unknownsreceived on the clk1 pin—to logic zero (0). Any unknowns received on clk1 are mappedto logic one (1).180 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsThese Signal Instance commands perform the same function as the Shell Softwareon_unknown statement, and the set_previous, set_low, set_high, and set_float attributesof the in_pin and io_pin statements. For more information, refer to the Shell SoftwareReference Manual. Note that explicit Shell Software settings override any SignalInstance commands.Unknown PropagationThe SIGnal INSTance propagate command turns on unknown propagation for allinstances of the selected components. The modeling system propagates the unknownsthrough the model using multi-sequence pattern play. The SIGnal INSTancenopropagate command turns off unknown propagation for all instances of the currentlyselected component, which is the default behavior.When unknown propagation is on, two pattern sequences are used by default. However,you can specify up to twenty additional sequences with the default_propagation -pnumber command, for a total of 22 sequences. You can also specify the value of the seedfor the random sequence generator with the random_seed -p seed command. The valueof the seed is 0 by default, but any number from 0 to 65,535 can be used.For example, you can issue the following:sig inst propagatesig inst default_propagation -p 8sig inst random_seed -p 7896These commands turn unknown propagation on for all instances of the selectedcomponents. The modeling system plays a total of ten sequences (the primary,secondary, and eight additional sequences) per instance to the device, and uses therandom sequence seed 7,896.These Signal Instance commands perform the same function as the Shell Softwareon_unknown statement. Note that explicit Shell Software settings override any SignalInstance commands, except for when the SIGnal INSTance nopropagate command isused. This exception allows the simulator to turn off unknown propagation if themodeling system is running out of pattern memory. For more information aboutunknown propagation, refer to the Shell Software Reference Manual and the LM-familyModeler Manual or the ModelSource User’s Manual.Indeterminate Strength MappingThe SIGnal INSTance is and SIGnal INSTance iz commands enable you to mapindeterminate strength pin values received on inputs of hardware models to either strong(hard) or high-impedance (float) strengths. The modeling system treats high-impedancestrength pin values as unknowns and maps or propagates them accordingly. By default,the system maps indeterminate strengths to strong strengths.October 6, 2003 Synopsys, Inc. 181

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideTest Vector LoggingThe SIGnal INSTance logvectors -p filename command turns on modeling system testvector logging for the selected instance. With test vector logging enabled, the inputs tothe device and sensed outputs from the device are stored to filename. By convention, thefilename used for the test vector output is device_name.VEC. The SIGnal INSTancenologvectors command turns off test vector logging for the selected instance, which isthe default behavior.For example, consider the following commands:sig inst logvectors -p '$ASIC2/vectors/vector11.VEC'dofile '$ASIC2/dofiles/run11.do'sig inst nologvectorsIn this example, the modeling system creates a test vector file called vector11.VEC.This file contains the vectors played to and sensed from the selected instance during thesimulation run by the dofile. The SIGnal INSTance nologvectors command turns off themodeling system test vector logging capability.After logging vectors, you can replay them directly to the device and note anydiscrepancies using the lm Play Vectors utility. This utility is particularly useful forASIC verification. For more information about ASIC verification and test vector (.VEC)file format, refer to the LM-family Modeler Manual or the ModelSource User’s Manual.Timing MeasurementThe SIGnal INSTance tm [-p filename] command turns on the modeling system timingmeasurement for the selected instance. The system then returns to the simulator theactual measured delay values for that instance. If you provide an optional filename, thesystem also saves the measured delays to a timing measurement (.TIM) file. Byconvention, device_name.TIM is the filename used for the timing measurement output.The SIGnal INSTance notm command turns off timing measurement for the selectedinstance, which is the default behavior. If timing measurement is disabled, theTechnology File delays (or the Shell Software delays if SIGnal INSTance lst isspecified) are returned to the simulator.For example, consider the following commands:sig inst tm -p '$ASIC2/timing/timing11.TIM'dofile '$ASIC2/dofiles/run11.do'sig inst notmIn this example, the modeling system creates a timing measurement file calledtiming11.TIM. This file contains the delays of the selected instance measured during thesimulation run created by the dofile. The SIGnal INSTance notm command turns off themodeling system timing measurement capability.182 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsThis Signal Instance command performs a similar function to that of the lm MeasureTiming utility. Timing measurement is particularly useful for ASIC verification. Formore information about ASIC verification and timing measurement (.TIM) file format,refer to the LM-family Modeler Manual or the ModelSource User’s Manual.NoteThe timing measurement (.TIM) file can be converted to a Shell Softwaredelays (.DLY) file by using the lm Create Timing File utility. (For moreinformation, refer to the LM-family Modeler Manual or the ModelSourceUser’s Manual.) The delays file can then be converted into a technology file,if desired, by using the lm_model utility with the -Step Timing option.Loop ModeThe SIGnal INSTance loop command turns on the modeling system pattern loopingcapability (loop mode) for the currently selected instance. In loop mode, the modelingsystem continually replays the complete pattern history of the selected instance to thedevice. The SIGnal INSTance noloop command turns off pattern looping.Pattern looping is a model development feature useful for analyzing the device behaviorand pattern history with an oscilloscope or logic analyzer connected to the device.However, while loop mode is enabled, no other user can access the modeling system;patterns are replayed to the selected device exclusively until loop mode is disabled. Forthis reason, QuickSim II returns an error if this command is specified when more thanone user is accessing the modeling system.Printing Model InformationA number of Signal Instance commands are available for printing information about theselected model instances. The SIGnal INSTance dump command prints all informationavailable about the currently selected instances, including:●●●Instance IDName of the modeling system in which the hardware model is locatedSetting for test vector logging (On or Off)● Setting for indeterminate strength mapping (S or Z)●●●Setting for Shell Software timing (On or Off)Model name, as specified in the Shell Software device_nameSetting for timing measurement (On or Off)October 6, 2003 Synopsys, Inc. 183

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration Guide●●Setting for loop mode (On or Off)Runtime vector count● Evaluation status (Enabled or Disabled)The SIGnal INSTance lmc and SIGnal INSTance vector commands print subsets of theinformation provided by SIGnal INSTance dump:●●The SIGnal INSTance lmc -p shell command prints the Shell Software timingsetting (On if you have specified SIGnal INSTance lst; Off if you have not) for theselected instances. SIGnal INSTance lmc -p allshell prints the Shell Software timingsetting for all hardware model instances, if you have at least one instance selected. Ifyou do not specify one of the -p arguments, this command will print a list of theavailable subcommands.The SIGnal INSTance vector command prints the runtime vector count of theselected instances.Performance MonitoringYou can monitor the performance of the hardware modeler and append the results to thesimulator log file after simulation. To enable performance monitoring, in the windowwhere you are running the simulator, enter the following:% setenv LM_OPTION “monitor_performance”For more information, refer to “Performance Monitoring” in the ModelSource User’sManual.Ending the Simulation SessionTermination of a normal simulation session notifies the hardware modeling system thatthe simulation session has ended. All modeling system resources being used by thatsimulation are then made available for other users.If the simulation exits abnormally, “orphaned” processes may exist on the modelingsystem, even though the simulation has terminated. If lmdaemon is running on yourworkstation, it automatically deletes orphaned processes. You can also use the lm AbortUser utility to remove the unwanted processes manually. Both of these methods releasemodeling system resources. (For more information about lmdaemon and the lm utilities,refer to the LM-family Modeler Manual or the ModelSource User’s Manual.)LM-family and ModelSource modeling systems support simulation save and restorecapabilities. When a save simulation state is performed, the state of all hardware modelsbeing used by the simulation session is automatically saved into a QuickSim II savedirectory. Similarly, restoring the simulation state automatically restores the state of themodel as used by the saved simulation, including all stored pattern history.184 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys ModelsAttentionIf you are using Shell Software that contains enhanced features—such asmodel state tracking or “when” conditions—the translation to the resultingtechnology file may be incomplete and contain “compromise” statements. Ifyou elect to use the technology file instead of the Shell Software duringsimulation, the device may exhibit incorrect timing and/or behavior. Toeliminate this possibility, translate the technology file from pre-R2.0 ShellSoftware, which does not contain these statements, or use the Shell Softwaredirectly during simulation by issuing the SIGnal INSTance lst command onthe hardware model instance. For more information about this procedure,refer to “Timing Shell Selection” on page 179.lm_model Command ReferenceThe lm_model shell command registers a hardware model by invoking hardware modelregistration and conversion programs.Syntaxlm_model input_dir [output_path] [-Dir name] [-Ifc interface] [-LAbel label][-Mdl mdl_filename] [-Step Register|Symbol|Timing|Update] [-Replace][-VERBose] [-Help] [-Usage] [-VERSion] [-Old] [-LM]Required Argumentinput_dirSpecifies the pathname to the directory containing the files tobe registered. This argument is required and must appear first.All pathname specifications use the following locationconvention:If the pathname is relative, the input_dir is assumed to be inthe working directory, as specified by $MGC_WD. If$MGC_WD is not set, the input_dir is assumed to be in thecurrent working directory.If the pathname starts with a dollar sign ($), the input_dir isassumed to be in the location of the location map variablespecified after the dollar sign.If the pathname is an absolute pathname, the input_dir isassumed to be in the location of the absolute pathname.October 6, 2003 Synopsys, Inc. 185

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideOptional Argumentsoutput_path-Dir name-Ifc interface-LAbel labelSpecifies the pathname to the directory that contains thecomponent information. If an output_path is not specified,then it defaults to the parent directory of the input_dir.Specifies just the new name of the output component directorywithin the output_path; for example, MC68020. By default,the name is created from the base name of input_dir byremoving any leading dollar ($) characters and converting alllowercase characters to uppercase. If the output componentdirectory name is the same as the input directory name,lm_model will generate an error and fail rather than overwritethe input directory.Specifies the component interface(s) with which to register themodel. Multiple component interfaces can be specified. Bydefault, the model is registered with all component interfaces.Specifies the label(s) to register with the component interface.Multiple labels can be specified. By default, the model isregistered with the $lm label, which corresponds to thefunctional description.-Mdl mdl_filename Specifies a particular model (.MDL) file within the input_dir.By default, the system uses the model file with the same basename as the output component directory, which is defined bythe -Dir switch.-Step Register|Symbol|Timing|Update-ReplaceSelects particular registration step(s):- Step Register registers the model’s functional description.- Step Symbol creates and registers the symbol.- Step Timing creates, compiles, and registers the technologyfile.- Step Update is equivalent to -Step Register and -StepTiming.By default, lm_model performs all the registration steps.Deletes the existing component directory and then recreates it.If you try to overwrite an existing symbol without using thisswitch, lm_model fails and generates an error message.186 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models-VERBose-Help-Usage-VERSion-Old-LMPrints additional messages while lm_model is executing.Prints help information on each of the available options, thenimmediately exits.Expands the command line and displays each argument andswitch. After printing the usage message, lm_modelimmediately exits.Prints the single-line version message, then immediately exits.Registers the model using the pre-V8.3 method, forcompatibility purposes.Does not affect lm_model execution. The system accepts thisargument for compatibility purposes.ExamplesThe lm_model utility provides several ways of specifying input and output files anddirectories. The following examples list a given input directory (model file) and desiredoutput component directory, and then show the lm_model command line you would useto get this result.Example 1Input directory: /user/models/74ls74 ($MGC_WD is set to /user/models)Model file: 74LS74.MDL (same as the component name)Component (output) directory: /user/models/74LS74 (default output path anddirectory)Command: lm_model 74ls74Example 2Input directory: /user/models/74ls74 ($MGC_WD is set to a directory other than/user/models)Model file: 74LS74A.MDL (different from the component name)Component (output) directory: /user/models/74LS74 (default output path anddirectory)Command: lm_model /user/models/74ls74 -m 74LS74AExample 3Input directory: /user/models/74ls74 ($MGC_WD is set to /user/models)Model file: 74LS74.MDL (same as the component name)October 6, 2003 Synopsys, Inc. 187

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration GuideComponent (output) directory: /user/project_xyz/74LS74 (default directory; nondefaultpath)Command: lm_model 74ls74 /user/project_xyzExample 4Input directory: /user/models/74ls74 ($MGC_WD is set to /user/models)Model file: 74LS74.MDL (same as the component name)Component (output) directory: /user/project_xyz/latch_7474 (non-default path anddirectory)Command: lm_model 74ls74 /user/project_xyz -d latch_7474tmg_to_ts Command ReferenceThe tmg_to_ts utility reads the Shell Software timing files to create a technology file.Comments from the Shell Software timing statements are not copied to the technologyfile. You must use the technology compiler (tc) to compile the technology file that iscreated by the tmg_to_ts utility before using the technology file in QuickSim II.In general, you should run the lm_model utility—which calls both tmg_to_ts and tc—rather than running the stand-alone tmg_to_ts utility. If you just want to update amodel’s Technology File, you can run lm_model with the -Step Timing option. For moreinformation on Technology File creation, refer to “Verifying the Technology File” onpage 174.Syntaxtmg_to_ts input_dir [-Out filename] [-Replace] [-Help] [-Usage] [-Version]Required Argumentsinput_dirSpecifies the pathname to the Shell Software timing files thatyou want to convert. If the input_dir is not a full path, it isassumed to be relative to the current directory, specified by$MGC_WD.Optional Arguments-Out filenameSpecifies an alternative filename for the output file. Bydefault, the output file is called technology.ts. All pathnamespecifications use the following location convention:188 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 7: Using QuickSim II with Synopsys Models-Replace-Help-Usage-VersionIf the pathname is a relative pathname, the output file is placedrelative to the component directory.If the pathname starts with period and slash (./), the output fileis placed in the current working directory as specified by$MGC_WD, if it exists.If the pathname starts with a dollar sign ($), the output file isplaced in the location of the location map variable specifiedafter the dollar sign.If the pathname is an absolute pathname, the output file isplaced in the location of the absolute pathname.Replaces the existing contents of the output directory with thenew output.Prints help information on each of the available options, thenimmediately exits.Expands the command line and displays each argument andswitch. After printing the usage message, tmg_to_tsimmediately exits.Prints the single-line version message, then immediately exits.October 6, 2003 Synopsys, Inc. 189

Chapter 7: Using QuickSim II with Synopsys ModelsSimulator Configuration Guide190 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys Models8Using Scirocco with SynopsysModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with Scirocco. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 191● “Using SmartModels with Scirocco” on page 193● “Using FlexModels with Scirocco” on page 196● “Using DesignWare Memory Models with Scirocco” on page 199● “Using Hardware Models with Scirocco” on page 201NoteScirocco has only 32-bit capabilities, and thus cannot simulate 64-bitSynopsys models.Setting Environment VariablesFirst, set the basic environment variables. In some cases the procedures that follow inthis chapter include steps for setting additional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installationOctober 6, 2003 Synopsys, Inc. 191

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide2. Set the SYNOPSYS_SIM variable to point to the Scirocco installation directory asfollows:% setenv SYNOPSYS_SIM Scirocco_installation_directory3. Source the environ.csh Scirocco environment file.% source $SYNOPSYS_SIM/admin/setup/environ.csh4. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variableto point to the product authorization file, as shown in the following example:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileYou can put license keys for multiple products (for example, SmartModels andhardware models) into the same authorization file. If you need to keep separateauthorization files for different products, use a colon-separated list (UNIX).CautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.5. If you are using the hardware modeler, set the LM_DIR and LM_LIB environmentvariables, as shown in the following examples:% setenv LM_DIR hardware_model_install_path/sms/lm_dir% setenv LM_LIB hardware_model_install_path/sms/models: \hardware_model_install_path/sms/mapsIf you put your models in a directory other than the default of /sms/models, modifythe above variable setting accordingly.Running 32-bit Models on 64-bit PlatformsIf you want to run 32-bit Synopsys models or tools on a 64-bit HP-UX or Solarisplatform, set the LMC_USE_32BIT environment variable to any value before invokingthe tool, as shown in the following example:% setenv LMC_USE_32BIT 1The LMC_USE_32BIT environmental variable is a “set/no-set” variable. That is, youcan set it to any value (even zero) to turn on 32-bit support on a 64-bit platform. If youdo not set it at all, the default condition is 32-bit models on 32-bit platforms, or 64-bitmodels on 64-bit platforms. You only set this environmental variable (to any value)when you are on a 64-bit platform using 32-bit models and simulators.192 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsUsing SmartModels with SciroccoTo use SmartModels with Scirocco, follow this procedure:1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. To create SmartModel VHDL templates, check to see if you have write permissionfor $LMC_HOME/synopsys/smartmodel; if so skip to Step 5. Otherwise, open thesynopsys_sim.setup file in your current working directory and search for the stringSMARTMODEL. By default, the logical library name SMARTMODEL is mappedto $LMC_HOME/synopsys/smartmodel, as follows:SMARTMODEL : $LMC_HOME/synopsys/smartmodel3. Change the directory to one where you have write permissions, as shown in thefollowing example:SMARTMODEL : ~/smartmodel4. Generate a VHDL model wrapper file for the model by invokingcreate_smartmodel_lib with any optional arguments. For complete information onthe syntax for this command, refer to “create_smartmodel_lib CommandReference” on page 194.% $SYNOPSYS_SIM/sim/bin/create_smartmodel_lib arguments5. If you changed the SMARTMODEL mapping in Step 3, you must use the -srcdiroption to specify that directory. Also, you can save time by using the -model or-modelfile option to specify the models you want. Otherwise, the script processes allinstalled SmartModels. For example, here is a recommended set of options to usefor one SmartModel (ttl00 in this example):% $SYNOPSYS_SIM/sim/bin/create_smartmodel_lib -model ttl00 \-srcdir ~/smartmodel6. After create_smartmodel_lib finishes executing, verify that the VHDL templatefiles were created in the appropriate directory.7. To use SmartModels in the VHDL source file of your design, specify theSMARTMODEL library and instantiate each SmartModel component. In the VHDLdesign file that uses SmartModel components, enter the following library and useclauses:library SMARTMODEL;use SMARTMODEL.components.allThe library logical name SMARTMODEL must be mapped to appropriatedirectories in your synopsys_sim.setup file.October 6, 2003 Synopsys, Inc. 193

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide8. Add the following line to your synopsys_sim.setup file:TIMEBASE = PS9. Instantiate SmartModels in your VHDL design. For information on requiredconfiguration parameters and instantiation examples, refer to “Using SmartModelswith SWIFT Simulators” on page 18.10. Compile your testbench as shown in the following example:% vhdlan testbench11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim designb. If you are using Scirocco 2000.12:% scsim designFor more information, refer to the Scirocco Reference Manual.create_smartmodel_lib Command ReferenceThe command reference for create_smarmodel_lib is as follows:Syntaxcreate_smartmodel_lib [--] [-nc] [-create] [-srcdir dirpath] [-analyze] [-nowarn][-modelfile file] {-model model_name}Arguments-- Displays the usage message and lists the command lineoptions.-nc-create-src_dir dirpathSuppresses the Synopsys copyright message.Creates the VHDL source files (.vhd files) for theSMARTMODEL library and saves the source files in the$LMC_HOME/synopsys directory.Lets you specify the location of the VHDL source files thatyou create. The default location is $LMC_HOME/synopsys.194 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys Models-analyze-nowarn-modelfile file-model model_nameAnalyzes the SMARTMODEL library source files (.vhd files)by invoking vhdlan. The analyzed files (.sim and .mra files)are saved in the $LMC_HOME/synopsys/smartmodeldirectory. This directory is specified by SMARTMODELlogical name mapping in the setup file.Suppresses the generation of warning messages that notifyyou of any port name mappings.A list of SMARTMODEL component names is read from file.Names are separated by spaces. Only the specified componentnames are included in the SMARTMODEL componentlibrary.The model_name is included in the resulting SMARTMODELcomponent library. Repeat this option to specify multiplemodels. Only specified component names are included in theSMARTMODEL component library.DescriptionWhen issued without options, the create_smartmodel_lib command takes all of the filesin the $LMC_HOME/models directory, creates and analyzes the VHDL template files,and saves them in the $LMC_HOME/synopsys/smartmodel directory. If you do nothave write permission for $LMC_HOME/synopsys/smartmodel, the commandterminates with an error message. In that case, you must use the -src_dir option tospecify a writable directory in which to place the VHDL templates. You must alsospecify that directory through the SMARTMODEL library mapping in the.synopsys_vss.setup file in your current working directory.October 6, 2003 Synopsys, Inc. 195

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration GuideUsing FlexModels with SciroccoTo use FlexModels with Scirocco, follow this procedure:1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. If you want the improved performance that comes with bused wrappers, generate aVHDL model wrapper file by invoking create_smartmodel_lib with any optionalarguments. For more information on the syntax for this command, refer to“create_smartmodel_lib Command Reference” on page 194.% $SYNOPSYS_SIM/sim/bin/create_smartmodel_lib argumentsNoteThe bused wrappers enable improved performance but do not work with theexamples testbench shipped with the model. To exercise the examplestestbench, use the wrappers shipped with the model (see Table 28), asexplained in the rest of this procedure. If you are using the bused wrappers,adjust accordingly.3. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 28 describes the FlexModel Scirocco interface andexample files that the flexm_setup tool copies.Table 28: FlexModel Scirocco VHDL FilesFile Name Description Locationmodel_pkg.vhdModel command procedure calls for HDLCommand Mode.workdir/src/vhdl/model_user_pkg.vhd Clock frequency setup and usercustomizations.workdir/src/vhdl/model_fx_vss.vhd A SWIFT wrapper for the model. workdir/examples/vhdl/model_fx_comp.vhdComponent definition for use with the modelentity defined in the SWIFT wrapper file. Thisis put in a package named “COMPONENTS”when compiled.workdir/examples/vhdl/196 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsTable 28: FlexModel Scirocco VHDL Files (Continued)File Name Description Locationmodel.vhdmodel_tst.vhdA bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench. This file assumes thatthe “COMPONENTS” package has beeninstalled in the logical library “slm_lib”.A testbench that instantiates the model andshows how to use basic model commands.workdir/examples/vhdl/workdir/examples/vhdl/4. Update the clock frequency supplied in the model_user_pkg.vhd file in yourworking directory to correspond to the desired clock period for the model. After yourun flexm_setup this file is located in:workdir/src/vhdl/model_user_pkg.vhdwhere workdir is your working directory.5. Add the following line to your .synopsys_vss.setup file:SLM_LIB : SLM_LIB_PATHTIMEBASE = PS6. Compile the FlexModel VHDL files into logical library slm_lib as follows:NoteThese examples provide details for event-based simulation. For informationon cycle-based operation, refer to the Scirocco Reference Manual.% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/flexmodel_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_user_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_pkg.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_fx_comp.vhd% vhdlan -w slm_lib workdir/src/vhdl/model_fx_vss.vhd% vhdlan -w slm_lib workdir/src/vhdl/model.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.October 6, 2003 Synopsys, Inc. 197

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide7. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement for the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;8. Instantiate FlexModels in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thesupplied bit-blasted wrapper (model_fx_vss.vhd).Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );9. Compile your testbench as shown in the following example:% vhdlan testbench10. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim -vhpi slm_vhpi:foreignINITelab:cpipeb. If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe design198 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsUsing DesignWare Memory Models withSciroccoDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx). To use DWMM modelswith Scirocco, follow these steps:1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. Create slm_lib and work directories, as shown in the following examples:% mkdir ./slm_lib% mkdir ./work3. Create the logical to physical mapping for the slm_lib, work, and default libraries bymodifying your local synopsys_sim.setup file to include the following lines:WORK > DEFAULTDEFAULT : ./workSLM_LIB : ./slm_lib4. Set your simulation timebase by modifying your local synopsys_sim.setup file toinclude a TIMEBASE entry, as shown in the following example:TIMEBASE = PS5. Compile the required Synopsys libraries into the slm_lib library, as shown in thefollowing example:% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/mempro_pkg.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.6. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.components.all;USE SLM_LIB.mempro_pkg.all;7. Create the model’s bused wrapper as shown in the following example:% $SYNOPSYS_SIM/platform/sim/bin/create_smartmodel_lib -create \-srcdir . -model model_mxThis step produces a components.vhd file and an entities.vhd file. The model_mxmodel is defined in the entities.vhd file.October 6, 2003 Synopsys, Inc. 199

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration Guide8. Instantiate the model_mx model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).9. Analyze the entities.vhd and components.vhd files, as shown in the followingexample:% vhdlan -w slm_lib components.vhd% vhdlan -w slm_lib entities.vhdNoteThese examples work for event-based simulation. For information on cyclebasedoperation, see the Scirocco Reference Manual.10. Analyze your testbench as shown in the following example:% vhdlan testbench.vhd11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim -vhpi slm_vhpi:foreignINITelab:cpipeb. If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe design200 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsUsing Hardware Models with SciroccoTo use Scirocco with hardware models, follow this procedure. Note that your design caninclude a mix of event-based and cycle-based, but hardware models simulate only asevent-based.1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. Add the hardware model install tree to your path variable, as shown in the followingexample:% set path=(/install_path/sms/bin/your_platform/ $path)3. Create the model.vhd wrapper file for your hardware model. You can use the nawkscript provided in “Scirocco Template Generator Script for Hardware Models” onpage 204 to generate this file. Copy the script and paste it into an executable filecalled hwm2vhdl.nawk.4. If you generate the wrapper by hand, you must provide:❍ an entity-architecture pair declaration so Scirocco can reference it in a latercomponent instantiation statement.❍a package for defining constants, declaring components, and instantiatingcomponents.5. Place the wrapper you just created in your testbench.6. Compile the wrapper and testbench you just created.% vhdlan hardwaremodel.vhd% vhdlan testbench7. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsimb. If you are using Scirocco 2000.12:% scsim designAttentionWhen using hardware models with Scirocco, your design can include a mixof event-based and cycle-based, but hardware models simulate only asevent-based.October 6, 2003 Synopsys, Inc. 201

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration GuideScirocco UtilitiesThe following hardware modeler simulator commands are supported in Scirocco.#lmsi list devices | idsYou can use the lmsi list devices command to list all hardware model instances bydevice name, and the lmsi list ids command to list all hardware model instances by idname. For example:# lmsi list devicesdevice name id# instance name loggingTILS299 0 /TB_TILS299/U0 Off# lmsi list idsid# device name instance name logging0 TILS299 /TB_TILS299/U0 OffYou can also log test vectors for the hardware model. To log by ID number, specify anid# and a filename. The extension .TST is appended to the vector file name. If no filename is specified, VSS writes to a file named device_name.id#.TST. For example:#lmsi logon id# filenameTo log vectors by instance name, specify an instance_name and filename. The extension.TST is appended to the output file name. For example:#lmsi logon instance_name filenameTo log vectors for all hardware model device instances, specify all. A log file is createdfor each instance. The output files are named device_name.id#.TST. For example:#lmsi logon allTo turn off vector logging, replace logon with logoff and omit the file name in the aboveexamples.VHDL Model Generics with SciroccoYou can also control hardware model behavior using VHDL generics in your hardwaremodel instantiations. The nawk script on page 204 creates VHDL wrappers forhardware models with these VHDL generics set to values that are reasonable for mostsimulations. However, you can modify the values of the VHDL generics in yourmodel.vhd files to suit your verification needs. For more information on supportedVHDL generics, refer to the Synopsys VHDL Simulation Interfaces Manual. Followingare descriptions of some of the most useful generics:202 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys ModelsLMSI_TIMING_MEASUREMENTYou can use the LMSI_TIMING_MEASUREMENT generic to direct where timingvalues for your simulation session come from. There are two legal values:ENABLEDThe hardware modeler measures and records actual pin-to-pintiming values and passes them to the simulator.DISABLEDThe hardware modelers passes to the simulator the pin-to-pintiming values from the .TMG file. This is the default value.LMSI_DELAY_TYPEYou can use the LMSI_DELAY_TYPE generic to specify whether the hardwaremodeler returns pin values to the simulator with minimum, typical, or maximum delays,as you can see in the following legal values:MINIMUMReturn minimum delays for pin values to the simulator.TYPICALMAXIMUMReturn typical delays for pin values to the simulator. This isthe default.Return maximum delays for pin values to the simulator.LMSI_LOGYou can use the LMSI_LOG generic to specify whether the hardware modeler logs testvector or not. There are two legal values:ENABLEDThe hardware modeler logs test vectors.DISABLEDThe hardware modelers does not log test vectors. This is thedefault value.October 6, 2003 Synopsys, Inc. 203

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration GuideScirocco Template Generator Script for Hardware ModelsHere is the nawk script that you can use to generate VHDL wrappers for the hardwaremodels. Because of the length this script, you will have to cut-and-paste one page at atime from this PDF file to get the whole thing copied to your environment.********************************************# In your design directory type:## nawk -f hwm2vhdl.nawk $HWM/.NAM > .vhd## (where "$HWM" is the full path to your hardware modeling directory)# Instantiate .vhd into your design.## THE SCRIPT:## Script to generate a VSS/Scirocco VHDL shell for a hardware model# using the .NAM fileBEGIN {pin_type = 0is_it_a_vector = "No"data_type = ""prev_signal = ""prev_test = ""prev_number = ""prev_dir = ""ending = ";"}printf "library SYNOPSYS;\n"printf " use SYNOPSYS.ATTRIBUTES.all;\n"printf "library IEEE;\n"printf " use IEEE.std_logic_1164.all;\n\n"$2 ~ /generic_device_name/ {device = $3printf "entity " device " is\n"printf " generic\n"printf " (\n"printf " timing : LMSI_TIMING_MEASUREMENT := DISABLED;\n"printf " delay_type : LMSI_DELAY_TYPE := TYPICAL;\n"printf " delay : LMSI_DELAY := ENABLED;\n"printf " log : LMSI_LOG := DISABLED;\n"printf " timing_violations : LMSI_TIMING_VIOLATIONS := DISABLED;\n"printf " xprop : LMSI_XPROP := DISABLED;\n"printf " xprop_method : LMSI_XPROP_METHOD := HIGH\n"printf " );\n\n"printf " port\n"printf " (\n"}$4 ~ /\(in_pin\)/ || $4 ~ /\(out_pin\)/ || $4 ~ /\(io_pin\)/ \|| $4 ~ /\(power_pin\)/ {pin_type++}204 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 8: Using Scirocco with Synopsys Models$2 ~ /\=/ || ($0 ~ /^$/ && pin_type ~ /3/) {if (pin_type == 1) {direction = "in "}else if (pin_type == 2) {direction = "out "}else if (pin_type == 3) {direction = "inout"}else {next}current_signal = $1 " "gsub(/\{/, "", current_signal)gsub(/\'/, "", current_signal)}current_test = current_signalgsub(/[0-9]+ /, " ", current_test)n = split(current_signal, array_a, "[a-zA-Z]")current_number = array_a[n]gsub(/ /, "", current_number)if (prev_signal ~ /[0-9]+ /) {if (current_test == prev_test) {if (is_it_a_vector == "No") {data_start = prev_number}if ((current_number == prev_number - 1) || (current_number == prev_number + 1)){is_it_a_vector = "Yes"}prev_signal = current_signalprev_test = current_testprev_number = current_numbernext}else {if (is_it_a_vector == "Yes") {total = prev_number + data_startif (prev_number > data_start) {data_end = data_startdata_start = prev_number}else {data_end = prev_number}data_type = "_vector (" data_start " " "downto " data_end ")"prev_signal = prev_test}}}if (prev_signal != "") {gsub(/ /, "", prev_signal)n = split(prev_signal, array_c, "[a-zA-z0-9_]")y = 20 - nif (y > 0) {for (i = 1; i

Chapter 8: Using Scirocco with Synopsys ModelsSimulator Configuration GuideEND {printf " );\n"printf "end " device ";\n\n"printf "architecture LMSI of " device " is\n"printf " attribute FOREIGN of LMSI : architecture is \"Synopsys:LMSI\";\n"printf " begin\n"printf "end LMSI;\n\n"}206 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models9Using VERA with Synopsys ModelsOverviewVERA is a testbench automation tool that works as a front-end to Verilog or VHDLsimulators. For general information on VERA, refer to:http://www.synopsys.com/products/veraThe procedures in this chapter are organized into the following major sections:● “Using VERA with FlexModels” on page 207● “Using VERA with DesignWare Memory Models” on page 223Using VERA with FlexModelsThis section explains how to use VERA with FlexModels, including a special section onhow to use VERA and VCS with FlexModels. This information is presented in thefollowing sections:● “Using FlexModels with the VERA UDF Interface” on page 208● “Creating a VERA Testbench” on page 210● “VERA Testbench Example” on page 211● “Incorporating FlexModels in a VERA Testbench” on page 213● “Using VERA with FlexModels and VCS” on page 215October 6, 2003 Synopsys, Inc. 207

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideUsing FlexModels with the VERA UDF InterfaceNoteVera 5.2.3 is not supported on HP-UX 10.20. FlexModels used with theVERA UDF Interface are built on HP-UX 11.0. So files from$LMC_HOME/lib/hp700.lib will not work for HP-UX 10.20FlexModels use the VERA user-defined functions (UDF) interface. UDFs are “bodies”(written in C) of VERA methods. They are much like Verilog, PLI, or VHDL functions.UDFs must be declared in a VERA header (.vrh) file to be usable by VERA programs.They must also be compiled and linked into the simulator executable.To use FlexModels with VERA, you need to build the VERA dynamic library. Buildingthe VERA dynamic library is a two step process:1. Compile the vera_user.c file to create vera_user.o.2. Link the object file for the simulator you are using (found in Table 30 on page 209),where the object file contains the compiled code for the UDF functions used byFlexModels.For more information on building the VERA dynamic library, refer to the UDFinformation in the VERA User Guide.AttentionIf you are building the VERA dynamic library for Verilog on Solaris, do notuse the -B symbolic. Using this switch results in unresolved symbolwarnings.Table 29 lists files you will need in order to build the VERA dynamic library.:Table 29: FlexModel Files Used with the VERA UDF InterfaceFile Name Description Locationvera_user.cvera_slm_pli.overa_slm_mti.oSource file containing table of UDFfunctions used by FlexModels.Object file for VCS and NC-VHDL. Thisfile contains the compiled code for the UDFfunctions used by FlexModels.Object file for MTI Verilog and MTIVHDL. This file contains the compiled codefor the UDF functions used by FlexModels.$LMC_HOME/sim/vera/src$LMC_HOME/lib/platform.lib$LMC_HOME/lib/platform.lib208 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsTable 29: FlexModel Files Used with the VERA UDF InterfaceFile Name Description Locationvera_slm_vhpi.o Object file for Scirocco. This file containsthe compiled code for the UDF functionsused by FlexModels.$LMC_HOME/lib/platform.liblibfmi_ar.almtv.oslm_pli.oObject file for NC Verilog. This filecontains the compiled code for the UDFfunctions used by FlexModels.This file contains the compiled code for theUDF functions used by SWIFT.This file contains the compiled code for theUDF functions used by Flex.$LMC_HOME/lib/platform.lib$LMC_HOME/lib/platform.lib$LMC_HOME/lib/platform.libAttentionYou need to re-build the VERA dynamic library whenever a new version ofVERA is introduced.Linking VERA with the SimulatorFor details on how to link VERA with individual simulators using the PLI, refer to theVERA User Guide. Table 30 lists the object files needed on the link line for the simulatoryou are using.Table 30: Link Line Object FilesSimulatorVCSNC-Verilogvera_slm_pli.o and vera_user.olmtv.o, slm_pli.o, and vera_user.oObject Files on the Link LineMTI Verilog vera_slm_mti.o and vera_user.oMTI VHDLNC-VHDLSciroccovera_slm_mti.o and vera_user.overa_user.o, sim_user.o, vera_slm_pli.o, and libfmi_ar.avera_user.o and vera_slm_vhpi.oIf you are using NC-VHDL, modify the $VERA_HOME/lib/nc_vhdl/sim_user.c, asfollows:1. Add the following line to the external declarations:October 6, 2003 Synopsys, Inc. 209

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guideextern fmiModelTableT CpipeModelTable;2. Add the following line to the fmiLibrary table:{ "Cpipe", CpipeModelTable },3. Compile the sim_user.c file to create the sim_user.o file.Creating a VERA TestbenchTo create a VERA testbench to use with FlexModels, follow these steps:1. Include the header files.Table 31 lists the two required header files.Table 31: VERA Header FilesFile Name Description Locationflexmodel_pkg.vrhmodel_pkg.vrhContains definitions for generic constantsuseful in FlexModel commands.Contains definitions for model class andmodel-specific constants useful inFlexModel commands.$LMC_HOME/sim/vera/src$LMC_HOME/models/model_fx/model_fxversion/src/vera2. Create an instance of the ModelFx (or ModelFz) class.Before using FlexModel commands, you must create an instance of the ModelFx orModelFz class in the VERA testbench.3. Send commands to a FlexModel through the model’s methods.In VERA Command Mode, you can use the same FlexModel features andcommands that you use in HDL Command Mode. There are a few differences incommand usage, however; refer to “Command Syntax Differences in VERACommand Model” in the FlexModel User’s Manual. For details on specificcommands, refer to “FlexModel Command Reference” in the FlexModel User’sManual.210 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsVERA Testbench ExampleThe following example shows how to incorporate FlexModels in a VERA testbench.#include #include “flexmodel_pkg.vrh”here#include “model_pkg.vrh”constants defined hereprogram model_test{// Vera Defines// FlexModel generic constants defined// Model class, and model-specific/** Create an instance of the model, argument 1 to the* constructor is the string name of the instance in* top level Verilog/VHDL testbench.* argument 2 is the path to the models clock pin* Here the assumption made is that the model is* instantiated in a Verilog testbench* Since the constructor has been called, this will* return at the next posedge of u1.CLK.*/ModelFx model_1 = new(“modelInstName_1”, “u1.CLK”);// Create another instance, since time has already elapsed// above, this call will return immediately.ModelFx model_2 = new(“modelInstName_2”, “u2.CLK”);// NOTE : This example assumes that the aguments to the// methods have been defined in the VERA testbench.// Check that no errors have occuredif ( model_1.showStatus() == FLEX_VERA_FATAL ||model_2.showStatus() == FLEX_VERA_FATAL ) {}// Errors exist, take suitable actionfork{// Send commands to the FlexModel Instance 1// Note that the id is encapsulated in the model// class and thus is not an argument to the commands.model_1.write(address1, data1, ‘FLEX_WAIT_F, status);model_1.write(address2, data2, ‘FLEX_WAIT_F, status);model_1.write(address3, data3, ‘FLEX_WAIT_F, status);October 6, 2003 Synopsys, Inc. 211

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guidemodel_1.write(address4, data4, ‘FLEX_WAIT_F, status);// Perform a read cyclemodel_1.read_req(address1, ‘FLEX_WAIT_F, status);model_1.read_req(address2, ‘FLEX_WAIT_F, status);model_1.read_req(address3, ‘FLEX_WAIT_F, status);model_1.read_req(address4, ‘FLEX_WAIT_F, status);// Get the read results back to the testbenchmodel_1.read_rslt(address1, tag, result1, status);model_1.read_rslt(address2, tag, result2, status);model_1.read_rslt(address3, tag, result3, status);model_1.read_rslt(address4, tag, result4, status);// Synchronize Instance 1 & 2// Note that the generic commands are also sent to// through the model’s instance.}{model_1.synchronize(2, “synch_2”, ‘timeout, status);// Send commands to the FlexModel Instance 2model_2.write(address1, data1, ‘FLEX_WAIT_F, status);model_2.write(address2, data2, ‘FLEX_WAIT_F, status);model_2.write(address3, data3, ‘FLEX_WAIT_F, status);// Synchronize Instance 1 & 2model_2.synchronize(2, “synch_2”, ‘timeout, status);}join // End of fork} // End of program model_test212 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsIncorporating FlexModels in a VERA TestbenchTo incorporate FlexModels in your VERA testbench, use the following procedure. Formore information on creating VERA interface files and using models in VERA, refer tothe VERA User Guide.1. Create a working directory and run flexm_setup to make copies of the model'sinterface and example files there, as shown in the following example:% $LMC_HOME/bin/flexm_setup -dir workdir model_fxYou must run flexm_setup every time you update your FlexModel installation witha new model version. Table 32 lists the files that flexm_setup copies to yourworking directory.Table 32: FlexModel VERA FilesFile Name Description Locationmodel_pkg.vrmodel_pkg.vrhContains FlexModel VERA class andmethod definitions.Contains model definitions for use inVERA testbenches.workdir/src/veraworkdir/src/vera2. Set the VERA_HOME variable to point to the location of your VERAinstallation directory:% setenv VERA_HOME path_to_VERA_installation3. Compile the VERA source files in the LMC_HOME tree.You need to compile three files: lstmodel.vr, swiftmodel.vr, and flexmodel_pkg.vr.The following is a sample compile script:% vera -cmp -I$LMC_HOME/sim/vera/src/lstmodel.vr% vera -cmp -I$LMC_HOME/sim/vera/src/swiftmodel.vr% vera -cmp -I$LMC_HOME/sim/vera/src/flexmodel_pkg.vrIf you are using VERA version 4.0 or earlier, you must compile theflexmodel_pkg.vr object with a “VERA_4” preprocessor flag. Your compile linewould therefore look like the following example:% vera -cmp -I$LMC_HOME/sim/vera/src/flexmodel_pkg.vr -DVERA_44. Compile the model’s VERA source file, model_pkg.vrThis file includes the flexmodel_pkg.vrh file, but the VERA compiler needs to findthe other header files too; therefore, you must include the path to the other headerfiles. The following is a sample compile script:% vera -cmp -I$LMC_HOME/sim/vera/src -Iworkdir/src/vera \workdir/src/vera/model_pkg.vrOctober 6, 2003 Synopsys, Inc. 213

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideNoteIf you are building the VERA dynamic library on Solaris, do not use the -Bsymbolic switch. Using this switch results in unresolved symbol warnings.5. Create a VERA testbench.For details, refer to “Creating a VERA Testbench” on page 210.6. Compile the VERA testbench.Although you need to include only the flexmodel_pkg.vrh and model_pkg.vrh filesin your VERA testbench, the VERA compiler needs to find the other header filestoo; therefore, you need to include the path to the VERA header files included inLMC_HOME. The following is a sample compile script:% vera -cmp -I$LMC_HOME/sim/vera/src -I/workdir/src/vera \vera_testbench.vrThis step produces two files: testbench.vro and testbench.vshell.7. Run the VERA testbench in a Verilog or VHDL simulation environment.When you run the Verilog or VHDL simulator, the VERA simulator needs to loadyour compiled VERA object files. You also need to load the following VERA objectfiles:• lstmodel.vro• swiftmodel.vro• flexmodel_pkg.vro• model_pkg.vro• testbench.vroFor more information on loading VERA object files, refer to the VERA User Guide.AttentionTo prevent your simulation from ending prematurely in cases where theVERA testbench completes before the Verilog/VHDL testbench, use the+vera_finish_on_end switch on your simulator invocation line.214 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsUsing VERA with FlexModels and VCSThis procedure explains how to use FlexModels with VERA and VCS. This is just oneway of using the VERA simulator's UDF, multiple .vro files, and so on. For moreinformation, refer to the VERA User Guide.1. Build the VERA dynamic library.Following are VERA dynamic library build examples for VCS 6.01 with VERA5.0.Solaris% /d/SUNWspro5/SUNWspro/bin/c89 -g -c \-I${VERA_HOME}/lib \${LMC_HOME}/sim/vera/src/vera_user.c% /usr/local/bin/ld -G -o vera_local.dl vera_user.o \${LMC_HOME}/lib/sun4Solaris.lib/vera_slm_pli.o \${VERA_HOME}/lib/vlog/libvlog_br.a \${VERA_HOME}/lib/libVERA.a \-lsocket -lnsl -lintl -lc -ldlHP-UX% /bin/c89 -c +z -I${VERA_HOME}/lib \${LMC_HOME}/sim/vera/src/vera_user.c% ld -b +e syssci_prod_entry +e errno \-o vera_local.dl vera_user.o \${LMC_HOME}/lib/hp700.lib/vera_slm_pli.o \${VERA_HOME}/lib/vlog/libvlog_br.a \${VERA_HOME}/lib/libVERA.a -lc -lmLinux% gcc -g -c -I${VERA_HOME}/lib ${LMC_HOME}/sim/vera/src/vera_user.c% gcc -shared -Bdynamic -o vera_local.dl vera_user.o \${LMC_HOME}/lib/x86_linux.lib/vera_slm_pli.o \${VERA_HOME}/lib/libVERA.a \${VERA_HOME}/lib/vlog/libvlog_br.aOctober 6, 2003 Synopsys, Inc. 215

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideSolaris% cc -DVERA_UDF -Kpic -c -I. -I$VERA_HOME/lib \$LMC_HOME/sim/vera/src/vera_user.c% ld -G -z text -o ./vera_local.dl ./vera_user.o \$LMC_HOME/lib/sun4Solaris.lib/vera_slm_pli.oHP-UXYou must use an ANSI standard compiler (for example, c89) for the followingexample to compile:% c89 -DVERA_UDF -c +Z -I$VERA_HOME/lib \$LMC_HOME/sim/vera/src/vera_user.c% ld -b +e Vera_UDF_Table \-o ./vera_local.dl ./vera_user.o \$LMC_HOME/lib/hp700.lib/vera_slm_pli.oLinux% gcc -c -DVERA_UDF -fPIC -I$VERA_HOME/lib \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o vera_local.dl vera_user.o \$LMC_HOME}/lib/x86_linux.lib/vera_slm_pli.o2. Modify the simv build.Modify the simv build by adding the following:❍❍❍-P ${VERA_HOME}/lib/vera_pli_dyn.tab${VERA_HOME}/lib/libSysSciTask.athe vshell file created when you compiled the VERA testbenchFor HP-UX add:-Mupdate=1 -gen_c -LDFLAGS “-W1, -E-W1, -a archive_shared” -ldld (mustcome before the -vera switch in simulation script.)For Linux add:-LDFLAGS "-rdynamic"For more information, refer to the installation and setup chapter in the VERA UserGuide.216 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsWith VERA 5.0 and VCS 6.01, two new VCS compile switches, (-vera and-vera_dbind, were added. These switches automatically link into the VERA libraryand include platform-specific VCS compiler switches. You need to use the+vera_udf=vera_local.dl switch when compiling with –vera or –vera_dbind. Fordetails please refer to VERA 5.0 Release Notes.The -vera switch can only be used for designs that do not use dynamic binding. Thismeans that the system clock has to be used in the FlexModel VERA interface. Touse the system clock, the model constructor must leave out the clk_path argumentand default to the system clock(new(InstName, “”))If a direct connection to the HDL clock is desired you must use the –vera_dbindswitch and specify the full path to the clock. The VERA interface then uses thesignal_connect function to perform dynamic binding.The model’s VERA interface will issue a warning, informing you that you havespecified a clock instead of using the default system clock. This warning can beswitched off by compiling the flexmodel_pkg.vr file with the -DNO_WARNINGpreprocessor flag.3. Create a file for VERA to load at runtime.This step assumes that the vro files are in the current working directory. You need tocreate a file that looks like the following example. The file name for this examplefile is files_to_load:./lstmodel.vro./swiftmodel.vro./flexmodel_pkg.vro./model_pkg.vro./testbench.vroFor more information, refer to the documentation on vera_mload in the VERA UserGuide.4. Run the simv executableAdd the +vera_udf and +vera_mload switches, as shown in the following example:% simv +vera_udf=./vera_local.dl +vera_mload = files_to_load \+vera_finish_on_endNoteThe +vera_finish_on_end switch prevents your simulation from endingprematurely in cases where the VERA testbench completes before theVerilog testbench.October 6, 2003 Synopsys, Inc. 217

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideExample Vera System Testbenches For FlexModelsA number of FlexModels have example Vera system testbenches. Ethernet, USB, andPCI-X models all have Vera testbenches. You will find the example testbenches in thefollowing directories:$LMC_HOME/models/pcimonitor_fx/pcimontior_fxVER/examples/vera$LMC_HOME/models/enethub_fx/enethub_fxVER/examples/vera$LMC_HOME/models/usbhost_fz/usbhost_fzVER/examples/veraThe Ethernet and USB models contain Synopsys provided make files to run thetestbench with various simulators. For PCI-X, the scripts to run the Vera testbench arelisted in the pcimonitor_fx datasheet.The make files in the USB in the Ethernet model directory and pcimonitor_fx datasheetshow how to run the Vera testbenches with the following simulators:●●●●VCSMTI-VerilogMTI-VHDLSciroccoFollowing is a listing of a make file to excute the Ethnernet FlexModel Vear testbenchusing the MTI VHDL simulator.218 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models################################################################# #### Makefile for compiling the vera_example test benches #### for ethernet flexmodels and running the simulation with #### MTI-VHDL simulator on SOLARIS platform. #### #### Note: This makefile intends to provide just a guideline #### and it is prepared using VERA-5.0 and ModelSim VHDL 5.5c #### for SunOS 5.6. #### Please refer to the latest manuals if needed for the #### correct settings if you are using other versions or #### environment. ################################################################### #### Note : Before compiliing or running simulation with #### this Makefile, following environment variables need #### to be set : #### #### LMC_HOME #### VERA_HOME #### MTI_HOME #### LM_LICENSE_FILE #### LD_LIBRARY_PATH (should include "./vera_out" in this case)#### LMC_LIB_DIR (Set to platform specific library in LMC_HOME;#### $LMC_HOME/lib/sun4Solaris.lib in this case) #### #### path : Add "$VERA_HOME/bin" to $path #### ################################################################### #### Steps to run simulation with this makefile : #### #### "make -f Makefile_mtivhd" (Default target) will run all #### the steps in a go. #### #### To compile and simulate in steps : #### 1. make -f Makefile_mtivhd initial #### 2. make -f Makefile_mtivhd compile_vera #### 3. make -f Makefile_mtivhd compile_vhdl #### 4. make -f Makefile_mtivhd run #### #### To clean the files created during this simulation, one of #### the very_clean, clean and vera_clean targets can be used #### as per the requirement. #### #### Note : By default, the half duplex system example test #### bench is simulated. To simulate full-duplex mode system #### test bench, override EXAMPLE_TB macro from command line #### as EXAMPLE_TB=full_duplex. #### ################################################################### Macros## This macro can be over-ridden as EXAMPLE_TB=full_duplex from# the command line to run the full-duplex mode example.October 6, 2003 Synopsys, Inc. 219

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideEXAMPLE_TB= half_duplex# utilitiesFLEXM_SETUP= ${LMC_HOME}/bin/flexm_setupMTI_BIN = ${MTI_HOME}/sunos5VLIB= ${MTI_BIN}/vlibVSIM= ${MTI_BIN}/vsimVCOM= ${MTI_BIN}/vcom# directories and filesOUT_DIR = ./vera_outSRC_DIR = ./examples/vera/testbench_files/half_duplexifeq ($(EXAMPLE_TB), full_duplex)SRC_DIR = ./examples/vera/testbench_files/full_duplexendifPROJ_FILE= ${SRC_DIR}/enetsys.proj# sourcesVERA_SRC = enetsys_mac1.vr enetsys_mac2.vr enetsys_media.vrVHDL_SRC = enetsys_MAC1_proj_shell.vhd \enetsys_MAC2_proj_shell.vhd \enetsys_media_proj_shell.vhd \${SRC_DIR}/test_top.vhd# optionsDESIGN_UNIT = cfgtopVERA_INC = -I${LMC_HOME}/sim/vera/src -I./src/veraVCOM_OPT = -93 -work slm_lib# miscVERA_OBJ = $(VERA_SRC:%.vr=%.vro)FLEXBASE_VR = lstmodel.vr swiftmodel.vr flexmodel_pkg.vrFLEXBASE_VROS = $(FLEXBASE_VR:%.vr=%.vro)PKG_VR= enettx_pkg.vr enetrx_pkg.vr enethub_pkg.vrifeq ($(EXAMPLE_TB), full_duplex)PKG_VR+= rmiirs_pkg.vrendifPKG_VROS= $(PKG_VR:%.vr=%.vro)## Targets## Default target which runs all the steps of initialization, compilation and simulationin a go.all : initial compile_vera compile_vhdl run# Perform the initial tasks before compiling and simulating the testbench.initial : flexm_setup link_dl $(OUT_DIR)/$(FLEXBASE_VROS) $(OUT_DIR)/$(PKG_VROS)220 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models# re/compile Vera testbench source files.compile_vera : $(OUT_DIR)/$(VERA_OBJ) proj# compile HDL shell files and top VHDL testbench file.compile_vhdl : slm_lib$(VCOM) $(VCOM_OPT) $(VHDL_SRC)# run the simulation. (check the environment and build the required files first).run : check_env ini ./vera.ini ./sim.cmdcp $(SRC_DIR)/*.dat .$(VSIM) -c -do sim.cmd -t ps -lib slm_lib $(DESIGN_UNIT)# copy useful files related to ethernet flexmodels from LMC_HOMEflexm_setup :$(FLEXM_SETUP) -dir ./ enettx_fx$(FLEXM_SETUP) -dir ./ enetrx_fx$(FLEXM_SETUP) -dir ./ enethub_fxifeq ($(EXAMPLE_TB), full_duplex)$(FLEXM_SETUP) -dir ./ rmiirs_fxendif# link together the dynamic library of the FlexModel command corelink_dl : $(OUT_DIR)/vera_user.old -G -z text -o $(OUT_DIR)/vera_mti.dl \${LMC_LIB_DIR}/vera_slm_mti.o \$(OUT_DIR)/vera_user.o \${VERA_HOME}/lib/mti/mti_bridge.a \${VERA_HOME}/lib/libVERA.a -lsocket -lnsl -lintl -lm -lc# compile the table of information about the FlexModel command core$(OUT_DIR)/vera_user.o :@mkdir -p $(OUT_DIR)/d/SUNWspro4/bin/c89 -K pic -c -I${VERA_HOME}/lib${LMC_HOME}/sim/vera/src/vera_user.c \-o $(OUT_DIR)/vera_user.o# compile the flex related vera files$(OUT_DIR)/$(FLEXBASE_VROS) :vera -cmp -q -I${LMC_HOME}/sim/vera/src ${LMC_HOME}/sim/vera/src/$(notdir$(@:.vro=.vr)) $(OUT_DIR)# compile _pkg.vr$(OUT_DIR)/$(PKG_VROS) :vera -cmp -q $(VERA_INC) ./src/vera/$(notdir $(@:.vro=.vr)) $(OUT_DIR)# compile testbench source vera files$(OUT_DIR)/$(VERA_OBJ) :vera -cmp -q -mti $(VERA_INC) $(SRC_DIR)/$(notdir $(@:.vro=.vr)) $(OUT_DIR)# Create Vera shell files for each testbench module listed in the project fileproj :vera -mti -proj $(PROJ_FILE)October 6, 2003 Synopsys, Inc. 221

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide# generate library slm_libslm_lib :@rm -rf slm_lib$(VLIB) slm_lib$(VCOM) $(VCOM_OPT) ${LMC_HOME}/sim/mti/src/slm_hdlc.vhd$(VCOM) $(VCOM_OPT) ${LMC_HOME}/sim/mti/src/flexmodel_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enethub_user_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enethub_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enettx_user_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enettx_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enetrx_user_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/enetrx_pkg.vhdifeq ($(EXAMPLE_TB), full_duplex)$(VCOM) $(VCOM_OPT) ./src/vhdl/rmiirs_user_pkg.vhd$(VCOM) $(VCOM_OPT) ./src/vhdl/rmiirs_pkg.vhdendif$(VCOM) $(VCOM_OPT) ./examples/vhdl/enethub_fx_mti.vhd$(VCOM) $(VCOM_OPT) ./examples/vhdl/enettx_fx_mti.vhd$(VCOM) $(VCOM_OPT) ./examples/vhdl/enetrx_fx_mti.vhdifeq ($(EXAMPLE_TB), full_duplex)$(VCOM) $(VCOM_OPT) ./examples/vhdl/rmiirs_fx_mti.vhdendif$(VCOM) $(VCOM_OPT) ${SRC_DIR}/enetsys_comp.vhd$(VCOM) $(VCOM_OPT) ./examples/vhdl/enethub.vhd$(VCOM) $(VCOM_OPT) ./examples/vhdl/enettx.vhd$(VCOM) $(VCOM_OPT) ./examples/vhdl/enetrx.vhdifeq ($(EXAMPLE_TB), full_duplex)$(VCOM) $(VCOM_OPT) ./examples/vhdl/rmiirs.vhdendif#check if LD_LIBRARY_PATH contains vera_outcheck_env :@if [ -z "`echo ${LD_LIBRARY_PATH} | grep "vera_out"`" ]; then \echo ""; \echo "LD_LIBRARY_PATH should contain ./vera_out (path to libvera_sro.so)"; \echo ""; \exit 1; \fi# generate the list of simulator commands../sim.cmd :@echo "run -all" > ./sim.cmd@echo "quit" >> ./sim.cmd# generate vera.ini./vera.ini :@echo "vera_pload=$(PROJ_FILE)" > ./vera.ini# Generate modelsim.ini if it does not exist.# Existance is checked to enable the user to use his own modelsim.ini# Therefore, modelsim.ini is also not removed in cleaning targets below.ini :@if [ ! -f modelsim.ini ]; then \echo "[Library]" > modelsim.ini; \222 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Modelsmodelsim.ini; \fiecho "slm_lib = ./slm_lib/" >> modelsim.ini; \echo "std = \$$MODEL_TECH/../std" >> modelsim.ini; \echo "ieee = \$$MODEL_TECH/../ieee" >> modelsim.ini; \echo "" >> modelsim.ini; \echo "[vsim]" >> modelsim.ini; \echo "PathSeparator = /" >> modelsim.ini; \echo "" >> modelsim.ini; \echo "[lmc]" >> modelsim.ini; \echo "libswift = \$$LMC_HOME/lib/sun4Solaris.lib/libswift.so" >># clean everything out.very_clean : clean@rm -rf $(OUT_DIR) src examples# clean the simulation related filesclean: vera_clean@rm -rf ./vera.ini ./sim.cmd slm_lib# clean just the vera compilation ("make compile_vera; make run" to rerun)vera_clean :@rm -rf *shell* $(OUT_DIR)/$(VERA_OBJ) transcriptUsing VERA with DesignWare MemoryModelsThis section explains how to use VERA with DesignWare Memory Models (DWMM).Standard DWMM models are binary simulation models, and have an _mx extension inthe model name: model_mx.This section contains the following topics:● “DesignWare Memory Models with VERA” on page 224●“Adding DesignWare Memory Model Commands to the VERA Testbench” onpage 230● “Building the VERA UDF Dynamic Library” on page 235● “Compiling the VERA Source Files” on page 242● “Building and Invoking the Simulator Executable” on page 244October 6, 2003 Synopsys, Inc. 223

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideDesignWare Memory Models with VERADesignWare Memory Models have an object-oriented VERA command interface youcan use to control the models from VERA, thereby retaining the benefits of the VERAverification language while using the DWMM testbench commands. For informationabout the DWMM VERA testbench commands, see the DesignWare Memory ModelUser’s Manual.DesignWare Memory Model VERA ClassesVERA implements a number of useful features of an object-oriented language. Thecustom DWMM-VERA interface provides a class that contains public method functionsso that a VERA testbench can access custom DWMM models. This class inherits thebase class LstModel features.Figure 9 shows the model hierarchy.LstModelCustomDWMMModelFigure 9: VERA Model Class HierarchyLstModel is an abstract or virtual class and cannot be instantiated directly in VERAtestbenches. Only an instance of a MemPro class can be created in a VERA testbench.The commands used to control DWMM models are public methods of the MemProclass. You can send DWMM models commands from VERA only through an instanceof the MemPro class.The following section refers often to user-defined functions (UDF). UDFs are “bodies”(written in C) of VERA methods. They are much like Verilog, PLI, or VHDL functions.UDFs must be declared in a VERA header (.vrh) file to be usable by VERA programs.They must also be compiled and linked into the simulator executable.224 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsKey DesignWare Memory Model VERA FilesThis section lists and describes files that are necessary for performing a VERAsimulation. Some are provided by Synopsys and are installed in your LMC_HOMEdirectory; others you must create.Table 33 lists and describes the key VERA files for DWMM models.Table 33: Key DesignWare Memory Model VERA FilesFilename Description Originvera_user.c avera_user.overa_slm_pli.overa_slm_mti.overa_slm_vhpi.overa_dyn_libraryA source file containing a table ofUDF functions used by DWMMmodels. You compile this for usein building the VERA dynamiclibrary.An object file containing a tableof UDF functions used byDWMM models. You use this inbuilding the VERA dynamiclibrary.An object file for SynopsysVCS. This file contains thecompiled code for the UDFfunctions used by DWMMmodels. You use this in buildingthe VERA dynamic library.An object file for MTIModelSim. This file contains thecompiled code for the UDFfunctions used by DWMMmodels. You use this in buildingthe VERA dynamic library.An object file for Scirocco. Thisfile contains the compiled codefor the UDF functions used byDWMM models. You use this inbuilding the VERA dynamiclibrary.This is the VERA dynamiclibrary, which is loaded duringsimulation. For instructions onloading this library, see the VERAUser Guide.Provided in your$LMC_HOME/sim/vera/srcdirectory.You create this file when youcompile vera_user.c.Provided in your$LMC_HOME/lib/platform.libdirectory.Provided in your$LMC_HOME/lib/platform.libdirectory.Provided in your$LMC_HOME/lib/platform.libdirectory.You create this file when youbuild the VERA dynamiclibrary; the name is arbitrary(for example, vera_local.dl)October 6, 2003 Synopsys, Inc. 225

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originmodel.{v, vhd}lstmodel.vrhmempromodel.vrhlstmodel.vrmempromodel.vrThe DWMM file for the modelyou want to instantiate.Note: You instantiate aDesignware Memory Model inyour HDL testbench using apositive integer in a quoted stringfor the ModelId parameter.Example: “67”But, you then use a true integer toinstantiate the same model in yourVERA testbench.Example: ( 67 )For more information on how toinstantiate standard DWMMmodels, see “Using DesignWareMemory Models with SWIFTSimulators” on page 29.For more information on how toinstantiate custom DWMMmodels, see “Instantiating CustomMemory Models” on page 285.A file containing the externalclass declaration for the LstModelclass. This file is included in themempromodel.vrh file.The mempromodel header file.Contains definitions for theMemPro model class and formodel-specific constants useful inDWMM memory commands. Youinclude this header in your VERAtestbench.A VERA source file containingthe LstModel class definition.You compile this file for useduring the simulation.A VERA source file containingtestbench commands, along withthe MemPro model classdefinition for model instantiation.You compile this file for useduring simulation.Generate wrappers forinstantiating the models asexplained in the simulatorspecificchapters in thismanual.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.Provided in your$LMC_HOME/sim/vera/srcdirectory.226 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsTable 33: Key DesignWare Memory Model VERA Files (Continued)Filename Description Originvera_testbench.vrThe user’s VERA testbench file,which creates MemPro classinstances and calls the DWMMtestbench methods.You compilethis file for use during simulation.You create this file with a texteditor.lstmodel.vromempromodel.vrovera_testbench.vrovera_shell.{v, vhd}design_testbench.top.{v,vhd}The object file after compilinglstmodel.vr. This file is usedduring simulation.The object file after compilingmempromodel.vr. This file is usedduring simulation.The object file after compilingvera_testbench.vr. This file isused during simulation.This file is the mediator betweenthe model and VERA, and is usedduring Verilog or VHDLcompilation.The top-level HDL testbench.This file is used during Verilog orVHDL compilation.You create this file when youcompile lstmodel.vr.You create this file when youcompile mempromodel.vr.You create this file when youcompile the VERA testbenchfile.This file is generated by VERAwhen you compile yourtestbench file.Create this file with a texteditor.design.{v, vhd} Your design. You created these files in orderto build your design.files_to_loadThis file contains the pathnamesof the VERA object fileslstmodel.vro, mempromodel.vro,and design_testbench.vro.Thesimulator looks in this file forVERA objects to load duringruntime.You create this file in a texteditor. The name is arbitrary.a. A vera_user.c file also exists in $VERA_HOME, but does not declare the MemPro andLstModel UDF functions, and does not work with DWMM. If you use a vera_user.c file otherthan the one provided in $LMC_HOME, make sure you include the function declarationsfound in the $LMC_HOME version.October 6, 2003 Synopsys, Inc. 227

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuidePrerequisites to Using the VERA with the DesignWareMemory Model InterfaceThe discussion of the VERA design flow assumes that you have already generated orobtained your memory models, have instantiated the models in your design, and havecreated both the top-level HDL testbench and the VERA testbench.Design Flow for DesignWare Memory Models with VERAFigure 10 on page 229 shows the design flow. First, add DWMM model commands tothe VERA testbench, vera_testbench.vr. Next, to be able to use the models with theVERA User-Defined Functions (UDF) interface, you must build a simulator-specificVERA dynamic library, to be linked into your simulator executable. Next, you compilethe VERA testbench, along with the Synopsys-supplied source files lstmodel.vr andmempromodel.vr, to obtain object files *.vro. In addition, the compile process generatesthe vera_shell.{v, vhd} file.Next, you build the simulator executable, linking in the HDL files (model.{v, vhd}, thetop-level HDL testbench, and vera_shell.{v, vhd}). Finally, you run the simulation.228 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Modelsvera_testbench.vrAdd DWMM Commands tothe VERA Testbenchvera_user.overa_testbench.vrvera_slm_pli.o | vera_slm_mti.o | vera_slm_vhpi.oBuild the VERA UDFDynamic Libraryvera_dyn_liblstmodel.vrmempromodel.vrvera_testbench.vrvera_shell.{v, vhd}Compile theVERA SourceBuild the SimulatorExecutablevera_shell.{v, vhd}vera_testbench.vrolstmodel.vromempromodel.vromodel.{v, vhd}files_to_loaddesign_testbench.top.{v, vhd}vera_dyn.lib will bedynamically loadedRun theSimulationFigure 10: DesignWare Memory Model with VERA Design FlowOctober 6, 2003 Synopsys, Inc. 229

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideAdding DesignWare Memory Model Commands to theVERA TestbenchThe following steps describe how to add DWMM model commands to a VERAtestbench so that you can use it with DWMM models.1. Open your VERA testbench in a text editor.2. To include the MemPro class in the mempromodel.vrh file, add the line:#include "mempromodel.vrh"after the line:#include 3. Create an instance of the MemPro class for each model in your design.To use the MemPro class methods, you must use the “new” constructor to create aMemPro object that maps to a DWMM model instance in your HDL design. The“new” constructor expects one integer argument, and the DWMM model instanceID, which is the numeric instance ID given to the DWMM model (in the Verilog orVHDL testbench). The constructor uses this argument to get an instance handle forthe DWMM model. If the instance ID passed is invalid, the model issues an errormessage and sets a flag in the class indicating the severity of the error.NoteAlways call inst.showStatus() after inst = new (inst_id); to ensure that theMemPro class constructor worked properly and that you provided the ID ofa DWMM model.The following example creates an instance of the VERA object connected to theHDL model with an instance ID of 67, and checks for errors.// 67 is the model instance id, defined in the// top-level HDL testbench.MemPro mem1 = new( 67 );if (mem1.showStatus()!= SLM_TESTBENCH_SUCCESS){//Error handlingexit(1);}You can then call DWMM testbench methods for object “mem1”.230 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models4. Send commands to a DWMM model through the model object’s testbench methods.The VERA testbench methods are similar to the SystemC testbench functions.However, there are some differences in the way they are called. TheVERA/DWMM testbench interface is implemented using the object-orientedfeatures of VERA. The testbench functions are available as methods of theMemPro class.The following example sets the message level to issue all messages.mem1.set_msg_level( SLM_ALL_MSGS, status);Note that the method does not take the model instance ID as an argument. Themem1 object stores its instance ID when it is constructed and therefore does notneed the instance ID when any of the testbench methods are called.For details on testbench setup, see the VERA User Guide.VERA Testbench ExampleThe following example shows DWMM models controlled from a VERA testbench.#define OUTPUT_EDGE PHOLD#define OUTPUT_SKEW #1#define INPUT_EDGE PSAMPLE#include #include "mempromodel.vrh"program DWMM_test{ // start of top block// global variablesinteger data_width, addr_width, status;string instance_name, class_name;bit[2047:0] tData;integer msgLevel;October 6, 2003 Synopsys, Inc. 231

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideMemPro mem1;//// Start of DWMM_test ////// Create an instance of the model with model_id = 5mem1 = new(5);if (mem1.showStatus()!= SLM_TESTBENCH_SUCCESS){printf (“Error: failure instantiating Model/n”);exit (1);}// Retrieve the instance infomem1.instance_info( data_width, addr_width, instance_name,class_name, status);printf( "instance_info status = %d\n", status);if (status == SIM TESTBENCH_SUCCESS) {printf( "Data_width = %d\n", data_width);printf( "Addr_width = %d\n", addr_width);printf( "Instance_name = %s\n", instance_name);printf( "Class_name = %s\n", class_name);}else {printf ("Error: Could not set info for mem1\n");exit();}// Set the message levelmem1.set_message_level( SLM_ALL_MSGS, status); }printf(" Set msg level status = %d\n", status);// Retrieve the message levelmem1.get_message_level( msgLevel, status);printf(" Get msg level status = %d\n", status);printf(" msg level = %d\n", msgLevel);if ( msgLevel != SLM_ALL_MSGS) {printf("Error: incorrect message level returned - %d\n",msgLevel);}// Poke some values into memorymem1.poke( 128'h00, 66'h1f, status);mem1.poke( 128'hFF, 66'hff, status);// Load a memory image filemem1.load( "./memory_images/sram1.mif", status);232 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models// Peek at some memory locationsmem1.peek( 128'hFF, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);mem1.peek( 128'h00, tData, status);printf(" Peek status = %d\n", status);printf(" Peek data = %h\n", tData);// Unload part of the memorymem1.unload( 128'ha0, 128'hff, status);// Dump the memory contents in Verilog formatmem1.dump( "./memory_images/sram2.mif", `SLM_FMT_VLOG, 128'h00,128'hffff, status);printf(" Dump status = %d\n", status);} // end of program DWMM_testA top-level HDL testbench file is required to connect your VERA testbench to theDWMM model. The following two VERA testbench examples show a VERA testbenchpaired with a Verilog testbench top module and a VERA testbench paired with a VHDLtestbench top module.VERA Testbench Paired with Top-level Verilog Testbench1. Top-level Verilog Testbench Examplemodule top;...am29f002bb_mx U1 (.a(a) , .dq(dq) , .we_n(we_n) , .ce_n(ce_n) ,.oe_n(oe_n), .reset_n(reset_n));// For DesignWare Memory Models, set ID of U1defparamU1.ModelId = “5”;2. VERA Testbench Exampleprogram model_test {MemPro inst1;}inst1 = new(5); // inst1 corresponds to U1 in Verilog testbenchif (inst1.showStatus()!= SLM_TESTBENCH_SUCCESS) {//Error handling}October 6, 2003 Synopsys, Inc. 233

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideVERA Testbench Paired with Top-level VHDL Testbench1. Top-level VHDL Testbench Exampleentity top if end top;architecture test of top is...U1 : am29f002bb_mx--For DesignWare Memory Models, set ID of U1generic map (ModelId => “5”)port map (a => adq => dqwe_n => we_noe_n => oe_nreset_n => reset_n);2. VERA Testbench Exampleprogram model_test {MemPro inst1;}inst1 = new(5); // inst1 corresponds to U1 in VHDL codeif (inst1.showStatus()!= SLM_TESTBENCH_SUCCESS){}//Error handling234 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsBuilding the VERA UDF Dynamic LibraryThe DWMM model with VERA testbench interface accesses DWMM internal testbenchcommands via the VERA User-Defined Functions (UDF) interface. In order to use themodels with VERA, you must build a dynamic library that contains the VERA UDFdeclarations for DWMM.When building the VERA dynamic library, you compile the vera_user.c file, and link aSynopsys-supplied object file (vera_slm_pli.o, vera_slm_mti.o, or vera_slm_vhpi.o) forthe simulator you are using.This section provides instructions for building a DWMM-compatible VERA UDFdynamic library. Except as noted, these instructions are compatible with these VERAversions:● VERA 5.1.1● VERA 5.2.3● VERA 6.0.0These instructions have been validated using these platform-specific compilers:OS Name OS Version Complier Compiler VersionHP-UX B.10.20 /bin/c89 A.10.32.20HP-UX B.11.00 (32-bit) /bin/c89 A.11.01.21505.GPLinux (Red Hat) 2.4.7–10 (7.2) gcc 2.95.3SunOs 5.6 /usr/ucb/cc 5.0SunOs 5.8 (32-bit) /usr/ucb/cc 5.0NoteThe compiler and linker options required to build a VERA UDF dynamiclibrary can vary depending upon your platform, compiler, linker,environmental settings, and any third-party software you may want tointegrate into your VERA testbench. See your VERA documentation forfurther information on building UDF dynamic libraries.October 6, 2003 Synopsys, Inc. 235

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideBuilding the VERA UDF Dynamic Library for MTI VHDLUse the following commands to build the VERA UDF dynamic library for MTI VHDLon your particular platform.NoteWhen using VERA version 5.1.1 on HP-UX, you must use the extension .slfor your locally created UDF library. Either create an appropriately namedsoft link to your local built UDF library:% ln -s ./vera_mti.dl vera_mti.slor use the correct extension for the output file name in the link command:% /usr/ccs/bin/ld -b -o ./vera_mti.sl ...HP-UXLinux% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./vera_mti.dl \./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_mti.o \$VERA_HOME/lib/mti/mti_bridge.a $VERA_HOME/lib/libVERA.a% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./vera_mti.dl \./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_mti.o \$VERA_HOME/lib/mti/mti_bridge.a $VERA_HOME/lib/libVERA.aSolaris% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./vera_mti.dl \./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_mti.o \$VERA_HOME/lib/mti/mti_bridge.a $VERA_HOME/lib/libVERA.a236 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsBuilding the VERA UDF Dynamic Library for MTI VerilogUse the following commands to build the VERA UDF dynamic library for MTI Verilogon your particular platform.NoteWhen using VERA version 5.2.3 or greater on the HP-UX, you may need tolink in libnsl (-L/usr/lib -lnsl) to avoid dynamic loading problems atruntime. If you are using VERA version 5.1.1 on HP-UX, do not include thelinker options -L/usr/lib -lnsl.HP-UXLinux% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_mti.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.a \-L/usr/lib -lnsl% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_mti.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.aSolaris% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_mti.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.aOctober 6, 2003 Synopsys, Inc. 237

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideBuilding the VERA UDF Dynamic Library for NC-VHDLTo use DWMM and VERA with NC-VHDL, you need to make a local copy of theVERA-specific sim_user.c, modify it to include the required DWMM FMI entries, thencompile and bind it into the your local libfmi library.NoteWhile DWMM does support NC-VHDL 4.0 (or greater), the VERAversions supported by DWMM do not support NC-VHDL 4.0 (or greater).All PlatformsPerform these steps first for all platforms.1. Make a local copy of the VERA-specific sim_user.c file:% cp $VERA_HOME/lib/nc_vhdl/sim_user.c .2. Edit the local copy of sim_user.c to add required DWMM FMI entries:a. Add the extern declaration for the required DWMM fmiModelTableT:extern fmiModelTableT CpipeModelTable;b. Add the DWMM fmiModelTableT entries into the global library table,fmiLibraryTable:{"Cpipe", CpipeModelTable}Your final file should resemble this typical VERA/DWMM-compatible sim_user.c file:#include extern fmiModelTableT vera_mtbl;extern fmiModelTableT CpipeModelTable;fmiLibraryTableT fmiLibraryTable = {{ "vera", vera_mtbl },{ "Cpipe", CpipeModelTable },{ 0, 0 },};From here, proceed to the next page to find instructions for you platform.238 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsHP-UXLinux% /bin/c89 -c +Z -I$CDS_INST_DIR/tools/inca/include -o ./sim_user.o \./sim_user.c% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./libfmi.sl \./sim_user.o ./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_pli.o \$VERA_HOME/lib/libVERA.a $VERA_HOME/lib/nc_vhdl/libVERAbr.a \$LMC_HOME/lib/hp700.lib/libfmi_ar.a% gcc -c -fPIC -I$CDS_INST_DIR/tools/inca/include -o ./sim_user.o \./sim_user.c% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./libfmi.so \./sim_user.o ./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_pli.o \$VERA_HOME/lib/libVERA.a $VERA_HOME/lib/nc_vhdl/libVERAbr.a \$LMC_HOME/lib/x86_linux.lib/libfmi_ar.aSolaris% /usr/ucb/cc -c -KPIC -I$CDS_INST_DIR/tools/inca/include -o ./sim_user.o \./sim_user.c% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./libfmi.so \./sim_user.o ./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_pli.o \$VERA_HOME/lib/libVERA.a $VERA_HOME/lib/nc_vhdl/libVERAbr.a \$LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.aOctober 6, 2003 Synopsys, Inc. 239

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideBuilding the VERA UDF Dynamic Library for NC-VerilogUse the following commands to build the VERA UDF dynamic library for NC-Verilogon your particular platform.HP-UXLinux% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_pli.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.a% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_pli.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.aSolaris% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_pli.o \$VERA_HOME/lib/vlog/libvlog_br.a $VERA_HOME/lib/libVERA.aBuilding the VERA UDF Dynamic Library for SciroccoUse the following commands to build the VERA UDF dynamic library for Scirocco onyour particular platform.HP-UXLinux% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./libvera_sro.sl \./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_vhpi.o \$VERA_HOME/lib/sro/sro_bridge.a $VERA_HOME/lib/libVERA.a% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./libvera_sro.so \./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_vhpi.o \$VERA_HOME/lib/sro/sro_bridge.a $VERA_HOME/lib/libVERA.a240 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsSolaris% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./libvera_sro.so \./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_vhpi.o \$VERA_HOME/lib/sro/sro_bridge.a $VERA_HOME/lib/libVERA.aBuilding the VERA UDF Dynamic Library for VCSUse the following commands to build the VERA UDF dynamic library for VCS on yourparticular platform.HP-UXLinux% /bin/c89 -c +Z -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ccs/bin/ld -b -o ./vera_local.dl./vera_user.o $LMC_HOME/lib/hp700.lib/vera_slm_pli.o% gcc -c -fPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% gcc -shared -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/x86_linux.lib/vera_slm_pli.oSolaris% /usr/ucb/cc -c -KPIC -I$VERA_HOME/lib -o ./vera_user.o \$LMC_HOME/sim/vera/src/vera_user.c% /usr/ucb/cc -G -z text -o ./vera_local.dl \./vera_user.o $LMC_HOME/lib/sun4Solaris.lib/vera_slm_pli.oOctober 6, 2003 Synopsys, Inc. 241

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideCompiling the VERA Source FilesDWMM models provide VERA source files that contain the classes and methods fromthe DWMM testbench interface. You must compile these files, along with your VERAtestbench that uses these methods, into object files (.vro) that are loaded by the simulatorat runtime.To compile the required VERA source files, follow these steps:1. Compile the VERA source files for the DWMM/VERA Testbench Interface.You need to compile two files: lstmodel.vr and mempromodel.vr. The following isa sample compile script:% vera -cmp $LMC_HOME/sim/vera/src/lstmodel.vr \-I$LMC_HOME/sim/vera/src% vera -cmp $LMC_HOME/sim/vera/src/mempromodel.vr \-I$LMC_HOME/sim/vera/src2. Compile the VERA testbench. You need to include the path to the VERA headerfiles in LMC_HOME, as shown in the following example for VCS:% vera -cmp vera_testbench.vr -I$LMC_HOME/sim/vera/srcFor details on compiling VERA source files with different simulators, see the VERAUser Guide.242 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsCreating a VERA List FileTo simulate your design with VERA, you need to specify the VERA object files to loadat simulation runtime. While VERA offers several mechanisms you can use for this (seeyour VERA documentation), this section uses a “VERA list file” that lists the paths ofthe VERA object files to load at runtime. (See your VERA manual for informationabout the various methods available for specifying VERA object files to load.)The following is an example of a typical VERA list file:./lstmodel.vro./mempromodel.vro./vera_testbench.vroTo use a VERA list file, you must provide your simulator with the path to the file. Theway you do this depends on your simulator:●●Some simulators support a command-line switch that lets you identify the path tothe list file when you invoke the simulator.Other simulators use a file named “vera.ini” to identify the path to the list file. Thevera.ini file must reside in the directory from which you invoke your simulator.Here is a typical vera.ini file:vera_mload=path_to_vera_list_fileTable 34 lists the simulators supported by DWMM, and the mechanism to use for eachto communicate the VERA list file path to the simulator.Table 34: VERA List File Path MechanismsSimulatorMTI VHDLMTI VerilogNC-VHDLNC-VLOGSciroccoVCSList File MechanismUse a vera.ini file.Use this command-line switch: +vera_mload=path_to_vera_list_fileUse a vera.ini file.Use this command-line switch: +vera_mload=path_to_vera_list_fileUse a vera.ini file.Use this command-line switch: +vera_mload=path_to_vera_list_fileOctober 6, 2003 Synopsys, Inc. 243

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideBuilding and Invoking the Simulator ExecutableThis section provides instructions for simulating DWMM models with VERA.Unless otherwise noted, these instructions are compatible with these versions of VERA:● VERA 5.1.1● VERA 5.2.3● VERA 6.0.0In addition, these instructions have been validated using these simulators and platforms:Table 35: Valid Simultators for Using DWMM Models with VERASimulatorVersionsModelSim VHDL 5.5c, 5.6dModelSim Verilog 5.5c, 5.6dNC-VHDL 3.1, 3.4NC-Verilog 3.1, 3.4Scirocco 2001.10, 2002.06VCS 6.1, 6.2Table 36: Valid Platforms for Using DWMM Models with VERAOSHP-UXHP-UXVersionsB.10.20B.11.00 (32-bit)Linux 2.4.7-10 (Red Hat Linux 7.2)SunOs 5.6SunOs5.8 (32-bit)VCS 6.1, 6.2244 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsNoteThe simulator compilation, elaboration, and/or runtime options required tobuild and run a VERA-compatible DWMM simulation can vary dependingon simulation requirements: platform differences, any custom PLI/FPI/CLIcode, your environmental settings, and any third-party tools you integrateinto your simulation. For further information, see your simulator, VERA, orthird-party documentation.Simulator: MTI VHDL1. Make sure MTI VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Modify your environmental library path to include the directory path to your localVERA UDF library, as follows:HP-UX:% setenv SHLIB_PATH dir_path_to_vera_mti.dl:$SHLIB_PATHLinux and Solaris:% setenv LD_LIBRARY_PATH dir_path_to_vera_mti.dl:$LD_LIBRARY_PATH3. Map the slm_lib logical library, as shown in the following example:% vlib slm_lib% vmap slm_lib slm_libThis step also creates a modelsim.ini file in the current working directory.4. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100psThen uncomment the libsm and libswift lines for the platform you are using:; ModelSim’s interface to Logic Modeling’s SmartModel SWIFT software;libsm = $MODEL_TECH/libsm.sl; libsm = $MODEL_TECH/libsm.dll; Logic Modeling’s SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling’s SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling’s SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling’s SmartModel SWIFT software (Sun4 SunOS); do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib; and run "vsim.swift".; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dllOctober 6, 2003 Synopsys, Inc. 245

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide5. To create the model’s bit-blasted VHDL wrapper, run the MTI sm_entity script, asshown in the following example:% $MTI_HOME/bin/sm_entity -c model_mx > model_mx.vhdThis step generates entity and component declarations for the model.NoteIf you want to use more than one DWMM model in your simulation, refer tothe “sm_entity Command Reference” on page 79.6. Edit the generated model_mx.vhd file as follows. In the architecture section, add the“library ieee” line highlighted in the following example:architecture SmartModel of model_mx isattribute FOREIGN : STRING;attribute FOREIGN of SmartModel : architecture is "sm_init$MODEL_TECH/libsm.sl ; model_mx;beginend SmartModel;library ieee; use ieee.std_logic_1164.all; package comp iscomponent model_mxAlso, at the end of the model_mx.vhd file, right after the “end component”statement, add the following highlighted line:end component;end comp;7. Compile the required Synopsys libraries into the slm_lib library, as shown in thefollowing examples:% vlib work% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/mempro_pkg.vhd8. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;USE SLM_LIB.comp.all;9. Compile the model’s bit-blasted wrapper file (model_mx.vhd) into the slm_liblibrary, as shown in the following example:% vcom -93 -work slm_lib model_mx.vhd10. Create a bused wrapper for the model, as shown in the following example:% $LMC_HOME/bin/vsg -bit2bus vhdl model_mxThis step produces an output file named model_mx_bw.vhd.246 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models11. Edit the model_mx_bw.vhd file to add Library and Use statements, as shown in thefollowing example:LIBRARY SLM_LIB;USE SLM_LIB.comp.all;12. Compile the model’s bused wrapper, as shown in the following example:% vcom -93 model_mx_bw.vhdAttentionTo use the bused model wrapper, you must add appropriate componentdeclarations to your testbench or edit a component file already included inyour testbench for multiple SWIFT models, specifying ports and generics asrequired.13. Instantiate the model in your design using either the bit-blasted wrapper(model_mx) or the bused wrapper (model_mx_bw). Define the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.14. Compile the VERA shell file created during the VERA compilation of your VERAtestbench, as follows:% vcom -93 _shell.vhdHintFor model-specific instantiation examples, see the individual modeldatasheets. You can copy the model instantiation directly from the modeldatasheet and paste it into your testbench. Be sure to map signal names in yourdesign to the model’s ports. You can access the model datasheet for yourmodel version using the sl_browser tool ($LMC_HOME/bin/sl_browser).15. Compile your testbench:% vcom -93 testbench.vhd16. Invoke MTI VHDL and simulate your design:% vsim testbench_configurationSimulator: MTI Verilog1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Build a local veriuser library as follows:October 6, 2003 Synopsys, Inc. 247

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideHP-UX:% /bin/c89 -DMTI -DaccVersionLatest -c +Z \-I$VERA_HOME/lib -I$MTI_HOME/include -o ./veriuser.o \$VERA_HOME/lib/veriuser.c% /usr/ccs/bin/ld -b -o ./veriuser.sl \./veriuser.o $VERA_HOME/lib/libSysSciTaskPIC.aLinux:% gcc -DMTI -DaccVersionLatest -c -fPIC \-I$VERA_HOME/lib -I$MTI_HOME/include -o ./veriuser.o \$VERA_HOME/lib/veriuser.c% gcc -shared -o ./veriuser.so \./veriuser.o $VERA_HOME/lib/libSysSciTaskPIC.aSolaris:% /usr/ucb/cc -DMTI -DaccVersionLatest -c -KPIC \-I$VERA_HOME/lib -I$MTI_HOME/include -o ./veriuser.o \$VERA_HOME/lib/veriuser.c% /usr/ucb/cc -G -z text -o ./veriuser.so \./veriuser.o $VERA_HOME/lib/libSysSciTaskPIC.a3. Modfiy your environmental library path to include the directory path to your localveriuser library, as follows:HP-UX:% setenv SHLIB_PATH dir_path_to_veriuser.sl:$SHLIB_PATHLinux and Solaris:% setenv LD_LIBRARY_PATH dir_path_to_veriuser.so:$LD_LIBRARY_PATH4. Set your SSI_LIB_FILES environmental variable to include the path to your localVERA UDF library, as follows:% setenv SSI_LIB_FILES path_to_vera_local.dl5. Map your work library as shown in this example:% vlib work% vmap work workThis produces a modelsim.ini file.6. Edit the modelsim.ini file to add a Resolution statement, as shown in this example:Resolution = 100ps248 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using SmartModels with ModelSim Verilog” onpage 61).7. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.8. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.9. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxThis step produces a bused Verilog wrapper file named model_mx_bw.v.10. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).11. Compile your design as shown in the following example:% vlog testbench.v model_mx.v model_mx_bw.v \vera_testbench_shell.v \+incdir+$LMC_HOME/sim/pli/srcOctober 6, 2003 Synopsys, Inc. 249

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide12. Invoke the simulator as shown in the following examples:HP-UX:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl designSolaris:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so designLinux:% vsim \+vera_mload=path_to_vera_list_file \-pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so designSimulator: NC-VHDL1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. Edit your cds.lib file to specify the logical library slm_lib for DWMM models:DEFINE slm_lib ./slm_libNoteAlso, make sure your cds.lib and hdl.var files contain the correctSOFTINCLUDE statements for running NC-VHDL.3. Create a directory named slm_lib:mkdir slm_lib4. Compile the required Synopsys libraries into the slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhdNoteIgnore the warning: ncvhdl_p: *W,FATSPB (slm_hdlc.vhd,72).% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd250 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsAttentionYou can omit steps 5 and 6, below, if you already performed those tasks asdescribed in “Using SmartModels with NC-VHDL” on page 109.5. Run the ncshell utility to generate a wrapper for the model you want to use:% ncshell -import swift -into vhdl model_mx -nocompile -work slm_libThis step produces in the slm_lib work directory a bit-blasted wrapper file(model_mx.vhd) and a component declaration file (model_mx_comp.vhd) for thespecified model.6. Compile the bit-blasted wrapper and component file:% ncvhdl -w slm_lib model_mx.vhd% ncvhdl -w slm_lib model_mx_comp.vhd7. If you want to use a bused wrapper for the model, do the following:a. Use the following command to produce a bused wrapper file namedmodel_mx_bw.vhd:% $LMC_HOME/bin/vsg -bit2bus vhdl model_mxb. Edit the model_mx_bw.vhd file to add Library and Use statements to the top ofthe file:LIBRARY SLM_LIB;USE SLM_LIB.smartmodels.all;c. Compile the bused wrapper:% ncvhdl -w slm_lib model_mx_bw.vhdAttentionIf you want to use the bused model wrapper, you must add appropriatecomponent declarations to your testbench or edit a component file alreadyincluded in your testbench for multiple SWIFT models, specifying ports andgenerics as required.8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.smartmodels.all;use slm_lib.mempro_pkg.all;October 6, 2003 Synopsys, Inc. 251

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration Guide9. Instantiate the model in your design using the bused wrapper (model_mx_bw) or thebit-blasted wrapper (model_mx). Define the ports, testbench pins, and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters, though you can override these values in your testbench ifneeded.For details on the required SWIFT parameters and DWMM instantiation examples,see “DesignWare Memory Model SWIFT Parameters” on page 29.Here is an example of a typical bused wrapper file:PORT MAP (a => sm_a,cs_n => sm_cs_n,be_n => sm_be_n,io => sm_io,oe_n => sm_oe_n,we_n => sm_we_n);SIGNAL sm_a : STD_LOGIC_VECTOR(17 DOWNTO 0);SIGNAL sm_cs_n : STD_LOGIC;SIGNAL sm_be_n : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_io : STD_LOGIC_VECTOR(16 DOWNTO 1);SIGNAL sm_oe_n : STD_LOGIC;SIGNAL sm_we_n : STD_LOGIC;SIGNAL sm_dout_valid : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL sm_wr_data : STD_LOGIC_VECTOR(0 TO 15);HintFor model-specific instantiation examples, see the model datasheets. Youcan cut and paste the instantiation directly from the model datasheet and intoyour testbench. Be sure to map signal names in your design to the model’sports. You can access the model datasheet for your version of the model withthe sl_browser tool ($LMC_HOME/bin/sl_browser).252 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsAttentionFor best performance, use version 4.0 or later of NC-VHDL. NC-VHDLversion 4 and higher allow you to load multiple dynamic libraries containingC code. To use this means of loading the DWMM routines, include thefollowing option in the line invoking ncsim:ncsim -loadfmi libfmi_ml.so:slm_boot libfmi_ml.so (or .sl on HP-UX platforms) contains the library table andbootstrap function needed by the dynamic loader included in NC-VHDLversion 4.0 and above. This method eliminates the need to link libfmi_ar.awith your other external C (foreign language) modules to produce a singlelibfmi.so that incorporates all foreign language modules in a single library.For more information about using the NC-VHDL with multiple dynamiclibraries, see your Cadence simulator documentation.Simulator: NC-Verilog1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. Copy the VERA specific veriuser.c file:% cp $VERA_HOME/lib/veriuser.c .3. Edit the local copy of the veriuser.c file to add the lines required for DWMM.a. Add the required DWMM include header and extern function declarations justbelow the VERA include header vmc_veri_funext.h:#include "ccl_lmtv_include.h"extern int pli_slm_post();extern int slm_mempro_handle();extern int slm_mempro_width_info();b. Add the DWMM s_tfcell entries to the global veriusertfs table:{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post", true },{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post_hdl", true },{ usertask, 0, 0, 0, slm_mempro_handle, 0, "$slm_mempro_handle", true },{ usertask, 0, 0, 0, slm_mempro_width_info, 0, "$slm_mempro_width_info", true },c. Add the required DWMM include code just below the VERA include codeentry vmc_veri_fundef.c:#include "ccl_lmtv_include_code.h"October 6, 2003 Synopsys, Inc. 253

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideHere’s an example of a combined VERA/DWMM-compatible veriuser.c file:/* README:To run Verilog 2.2 only with Vera, use this veriuser.c as is.For other versions of Verilog you may need to edit this template.If you need to link in additional tasks, you will need to combinethis veriuser.c with your own (if you have not done this before,please see the directions in Cadence's documentation).*/#ifdef WIN32# define Dll_Export __declspec(dllexport)#else# define Dll_Export#endif#include "veriuser.h"#include "acc_user.h"#ifndef accVersionLatest#include "vxl_acc_user.h"#include "vxl_veriuser.h"#endif#include "vmc_veri_funext.h"#include "ccl_lmtv_include.h"extern int pli_slm_post();extern int slm_mempro_handle();extern int slm_mempro_width_info();Dll_Export char *veriuser_version_str ="=== Verilog with Synopsys Vera ===\n";Dll_Export bool err_intercept(level,facility,code)int level;char *facility;char *code;{return(true);}Dll_Export s_tfcell veriusertfs[] ={/*** Template for an entry:* { usertask|userfunction, data,* checktf(), sizetf(), calltf(), misctff(),* "$tfname", forwref?, Vtool?, ErrMsg?* },254 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models* Example:* { usertask, 0, my_check, 0, my_func, my_misctf, "$my_task"* },* ***/{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post", true },{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post_hdl", true },{ usertask, 0, 0, 0, slm_mempro_handle, 0, "$slm_mempro_handle", true },{ usertask, 0, 0, 0, slm_mempro_width_info, 0, \"$slm_mempro_width_info", true },# include "vmc_veri_fundef.c"#include "ccl_lmtv_include_code.h"/*** add user entries here ***/{0} /*** final entry must be 0 ***/};Dll_Export void init_usertfs(){p_tfcell usertf;for (usertf = veriusertfs; usertf; usertf++){if (usertf->type == 0)return;mti_RegisterUserTF(usertf);}}#endifDll_Export int (*endofcompile_routines[])() ={/*** my_eoc_routine, ***/0 /*** final entry must be 0 ***/};4. Build a local libpli library as follows:HP-UX:% /bin/c89 -c +Z -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% /usr/ccs/bin/ld -b -o ./libpli.sl \./veriuser.o $LMC_HOME/lib/hp700.lib/lmtv.o \$LMC_HOME/lib/hp700.lib/slm_pli_dyn.sl $VERA_HOME/lib/libSysSciTaskPIC.aOctober 6, 2003 Synopsys, Inc. 255

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideLinux:% gcc -c -fPIC -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% gcc -shared -o ./libpli.so \./veriuser.o $LMC_HOME/lib/x86_linux.lib/lmtv.o \$LMC_HOME/lib/x86_linux.lib/slm_pli_dyn.so $VERA_HOME/lib/libSysSciTaskPIC.aSolaris:% /usr/ucb/cc -c -KPIC -I$LMC_HOME/include -I$VERA_HOME/lib/vlog \-I$CDS_INST_DIR/tools/inca/include -o ./veriuser.o ./veriuser.c% /usr/ucb/cc -G -z text -o ./libpli.so \./veriuser.o $LMC_HOME/lib/sun4Solaris.lib/lmtv.o \$LMC_HOME/lib/sun4Solaris.lib/slm_pli_dyn.so $VERA_HOME/lib/libSysSciTaskPIC.a5. Modify your environmental library path to include the directory path to your locallibpli library, as follows:HP-UX:% setenv SHLIB_PATH dir_path_to_libpli.sl:$SHLIB_PATHLinux and Solaris:% setenv LD_LIBRARY_PATH dir_path_to_libpli.so:$LD_LIBRARY_PATH6. Set your SSI_LIB_FILES environmental variable to include the path to yourlocal VERA UDF library, as follows:% setenv SSI_LIB_FILES path_to_vera_local.dl7. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.8. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.9. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxThis step produces a bused Verilog wrapper file named model_mx_bw.v.256 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys Models10. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).11. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.12. Invoke NC-Verilog to compile and simulate your design, as shown in the followingexample:% ncverilog \model_mx.v \model_mx_bw.v \testbench.v \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w13. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var14. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib model_mx.v model_mx_bw.v tsetbench.v \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchOctober 6, 2003 Synopsys, Inc. 257

Chapter 9: Using VERA with Synopsys ModelsSimulator Configuration GuideSimulator: Scirocco1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. Create slm_lib and work directories, as shown in the following examples:% mkdir ./slm_lib% mkdir ./work3. Create the logical to physical mapping for the slm_lib, work, and default libraries bymodifying your local synopsys_sim.setup file to include the following lines:WORK > DEFAULTDEFAULT : ./workSLM_LIB : ./slm_lib4. Set your simulation timebase by modifying your local synopsys_sim.setup file toinclude a TIMEBASE entry, as shown in the following example:TIMEBASE = PS5. Compile the required Synopsys libraries into the slm_lib library, as shown in thefollowing example:% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/mempro_pkg.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.6. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.components.all;USE SLM_LIB.mempro_pkg.all;7. Create the model’s bused wrapper as shown in the following example:% $SYNOPSYS_SIM/platform/sim/bin/create_smartmodel_lib -create \-srcdir . -model model_mxThis step produces a components.vhd file and an entities.vhd file. The model_mxmodel is defined in the entities.vhd file.8. Instantiate the model_mx model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.258 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 9: Using VERA with Synopsys ModelsHintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).9. Analyze the entities.vhd and components.vhd files, as shown in the followingexample:% vhdlan -w slm_lib components.vhd% vhdlan -w slm_lib entities.vhdNoteThese examples work for event-based simulation. For information on cyclebasedoperation, see the Scirocco Reference Manual.10. Analyze your testbench as shown in the following example:% vhdlan testbench.vhd11. Invoke the Scirocco simulator as shown in the following examples:a. If you are using Scirocco 2001.10 or later:% scs design% scsim -vhpi slm_vhpi:foreignINITelab:cpipeb. If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe designOctober 6, 2003 Synopsys, Inc. 259

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Simulator Configuration GuideChapter 10: Using SystemC with Synopsys Models10Using SystemC with SynopsysModelsOverviewThis chapter explains how to use SmartModels and DesignWare Memory Models withSystemC. The procedures are organized into the following major sections:● “Setting Environment Variables” on page 261● “Using SmartModels with SystemC” on page 262● “Using DesignWare Memory Models with SystemC” on page 264Setting Environment VariablesBegin by setting environment variables as follows.1. Set the LMC_HOME environment variable to point to your SmartModel orDWMM installation tree, as follows:% setenv LMC_HOME path_to_models_installation2. Set the LM_LICENSE_FILE (for SmartModels) or SNPSLMD_LICENSE_FILE(for DWMM models) environment variable to point to the product authorizationfile, as shown in these examples:% setenv LM_LICENSE_FILE path_to_product_authorization_file% setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_fileIf needed, you can put license keys for multiple products into the same authorizationfile. If you need to keep separate authorization files for different products, use acolon-separated list to specify the search path in your variable setting.October 6, 2003 Synopsys, Inc. 261

Chapter 10: Using SystemC with Synopsys ModelsSimulator Configuration GuideCautionDo not include la_dmon-based authorizations in the same file with snpslmdbasedauthorizations. If you have authorizations that use la_dmon, keepthem in a separate license file that uses a different license server (lmgrd)process than the one you use for snpslmd-based authorizations.3. Make sure your SystemC environment is properly set up — see your SystemCinstallation documentation for details.Using SmartModels with SystemCTo use SmartModels with SystemC, follow this procedure:1. Run the scsg utility to generate SystemC wrappers for the models you will use inyour design.To generate wrappers, enter the model names (separated by spaces) as arguments toscsg:% $LMC_HOME/bin/scsg model model2For each specified model, this creates the wrapper files model.h and model.cppwithin the working directory.The scsg command also includes two optional switches:❍ -a or --all: Generates wrappers for all installed models.❍ -r or --resolved: Generates wrappers using resolved logic vectors (typesc_signal_rv) for the model port interface. The default is togenerate a port interface using the sc_logic type for single bitports, and type sc_lv for bus ports.2. Instantiate the model in your design using the model wrapper model.h file as aguide:❍❍❍Include the header file for each SmartModel in your design.Example: #include “model.h”Assign values to the model’s SmartModel SWIFT parameters (modelconfiguration parameters).If needed, bind the model’s ports to system level signals.262 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 10: Using SystemC with Synopsys ModelsThe model.h wrapper file includes an example of instantiating the model withdefault values for the required model configuration parameters. For details on therequired SmartModel SWIFT parameters, see “Using SmartModels with SWIFTSimulators” on page 18.3. Modify your SystemC build environment to compile and link the models in yourdesign, and to link in the runtime support library:a. Add the following to the list of include directories used by your compiler:• The location of the model.h wrappers generated in step 1.• $LMC_HOME/includeExample: $CC -I$LMC_HOME/include -Imodel_wrapper_dir...b. Modify the list of source files compiled for your design to include themodel.cpp file generated in step 1 for each model in the design.Example: $CC -c model.cpp...c. Add the following to the list of object files linked into your design’s executable:• Each of the model interface objects compiled in step 3b.• The SWIFT SystemC interface library:– On Solaris: $(LMC_HOME)/lib/sun4Solaris.lib/libscswift.a– On Linux: $(LMC_HOME)/lib/x86_linux.lib/libscswift.aExample: $LD... $(LMC_HOME)/lib/sun4Solaris.lib/libscswift.a model.cpp...4. Compile your SystemC design.5. Link your SystemC executable.6. Run your SystemC executable.October 6, 2003 Synopsys, Inc. 263

Chapter 10: Using SystemC with Synopsys ModelsSimulator Configuration GuideUsing DesignWare Memory Models withSystemCDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (model_mx.)To use DWMM models with SystemC, follow this procedure:1. Run the scsg utility to generate SystemC wrappers for the models you will use inyour design.To generate wrappers, enter the model names (separated by spaces) as arguments toscsg:% $LMC_HOME/bin/scsg model model2For each specified model, this creates the wrapper files model.h and model.cppwithin the working directory.The scsg command also includes two optional switches:❍ -a or --all: Generates wrappers for all installed models.❍ -r or --resolved: Generates wrappers using resolved logic vectors (typesc_signal_rv) for the model port interface. The default is togenerate a port interface using the sc_logic type for single bitports, and type sc_lv for bus ports.2. Instantiate the model in your design using the model wrapper model.h file as aguide:❍❍❍Include the header file for each DWMM model in your design.Example: #include “model.h”Assign values to the model’s DWMM SWIFT parameters (model configurationparameters).If needed, bind the model’s ports to system level signals.The model.h wrapper file includes an example of instantiating the model withdefault values for the required model configuration parameters. For details on therequired DWMM parameters and an example of instantiating an DWMM model inSystemC, see “Using DesignWare Memory Models with SWIFT Simulators” onpage 29 and “Instantiating DesignWare Memory Models in SystemC” on page 35.264 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideChapter 10: Using SystemC with Synopsys Models3. Modify your SystemC build environment to compile and link the models in yourdesign, and to link in the runtime support library:a. Add the following to the list of include directories used by your compiler:• The location of the model.h wrappers generated in step 1.• $LMC_HOME/includeExample: $CC -I$LMC_HOME/include -Imodel_wrapper_dir...b. Modify the list of source files compiled for your design to include themodel.cpp file generated in step 1 for each model in the design.Example: $CC -c model.cpp...c. Add the following to the list of objects files linked into your design’sexecutable:• Each of the model interface objects compiled in step 3b.• The SWIFT SystemC interface library:– On Solaris: $(LMC_HOME)/lib/sun4Solaris.lib/libscswift.a– On Linux: $(LMC_HOME)/lib/x86_linux.lib/libscswift.aExample: $LD... $(LMC_HOME)/lib/sun4Solaris.lib/libscswift.a model.cpp...4. Compile your SystemC design.5. Link your SystemC executable.6. Run your SystemC executable.October 6, 2003 Synopsys, Inc. 265

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Simulator Configuration GuideAppendix A: Using LMTV with Synopsys ModelsAUsing LMTV with Synopsys ModelsWhat is LMTV?LMTV stands for Logic Models to Verilog. This appendix is devoted to LMTV, and isnot about one simulator, like most chapters in this book. Instead, LMTV is a PLIapplication that is used to interface SmartModels, FlexModels, and DesignWareMemory Models with NC-Verilog and MTI Verilog. Note that VCS uses the SWIFTinterface and not LMTV.This appendix provides user and reference information for LMTV in the followingmajor sections:● “Static Linking with LMTV” on page 268● “LMTV Command-Line Switches” on page 270● “LMTV Commands” on page 271October 6, 2003 Synopsys, Inc. 267

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration GuideStatic Linking with LMTVSynopsys provides LMTV in the form of dynamically loadable libraries for NC-Verilogand MTI-Verilog. This is generally the preferred method for using LMTV. If you areusing NC-Verilog and cannot use the Synopsys-supplied swiftpli shared library, refer tothe Cadence documentation for information on using the PLIWizard to build your ownPLI library. If you are using MTI Verilog, and cannot use the Synopsys-suppliedswiftpli_mti shared library, refer to the MTI documentation for information on buildingyour own PLI and locating it for the simulator. Synopsys still ships the files needed tobuild your own PLI. These include:●●●Edited copy of veriuser.c in the $LMC_HOME/sim/pli/src directory (see Editedveriuser.c File)LMTV object file (lmtv.o) in the $LMC_HOME/lib/platform.lib directoryC-Pipe object file (slm_pli.o), in the $LMC_HOME/lib/platform.lib directoryNoteThe C-Pipe is required for FlexModels and DesignWare Memory Models,but is not needed for regular SmartModels.Edited veriuser.c FileHere is an example of the edited veriuser.c file that is shipped in the$LMC_HOME/sim/pli/src directory. The edits that are required for Synopsys modelsare highlighted. If you build your own PLI and want to use Synopsys models, be sure toadd these highlighted lines to your veriuser.c file.#include "veriuser.h"#include "vxl_veriuser.h"#include "ccl_lmtv_include.h"/************************************//* extern PLI function declarations *//************************************//* ------------- cut here - section 1 -------------- *//* C-pipe interface */extern int pli_slm_post();extern int slm_mempro_handle();extern int slm_mempro_width_info();extern int slm_transport();extern int slm_transport_checktf();extern int slm_inertial();extern int slm_inertial_checktf();/* ------------- end section 1 -------------- */268 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys Modelschar *veriuser_version_str = "";int (*endofcompile_routines[TF_MAXARRAY])() ={/*** my_eoc_routine, ***/0 /*** final entry must be 0 ***/};bool err_intercept(level,facility,code)int level; char *facility; char *code;{ return(true); }s_tfcell veriusertfs[TF_MAXARRAY] ={/*** Template for an entry:{ usertask|userfunction, data,checktf(), sizetf(), calltf(), misctf(),"$tfname", forwref?, Vtool?, ErrMsg? },Example:{ usertask, 0, my_check, 0, my_func, my_misctf, "$my_task" },***//*** add user entries here ***/#include "ccl_lmtv_include_code.h"/* ------------- cut here - section 2 -------------- */{ usertask, 0, 0, 0, pli_slm_post, 0,"$slm_post_hdl", true },{ usertask, 0, 0, 0, pli_slm_post, 0, "$slm_post",true },{ usertask, 0, 0, 0, slm_mempro_handle, 0,"$slm_mempro_handle", true },{ usertask, 0, 0, 0, slm_mempro_width_info, 0,"$slm_mempro_width_info", true },{ usertask, 0, slm_transport_checktf, 0, slm_transport, 0,"$slm_transport", true },{ usertask, 0, slm_inertial_checktf, 0, slm_inertial, 0,"$slm_inertial", true },/* ------------- end section 2 -------------- */};{0} /*** final entry must be 0 ***/October 6, 2003 Synopsys, Inc. 269

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration GuideLMTV Command-Line SwitchesLMTV command-line switches have a session-wide scope that impacts all SmartModelinstances. Notice that the +laiobj switch, used by the LAI interface, is not used in eithermode of the LMTV interface. Following are brief descriptions for each of the commandlineswitches that you can use with LMTV:+notimingchecks+[min | typ | max]delays+lmudtmsg or +laiudtmsg+lmoldstr+lmoldtrans+lmresstrDisables timing checks (for example, setup and holdtimes) and their accompanying messages. The defaultis to perform the timing checks.Specifies a single delay range for all model instances.The default is to use the delay range in the model’sDelayRange or RANGE attributes.Generates a list of the timing files loaded at simulationstartup. This is equivalent to setting the commandchannel command TraceTimeFile to ON. The default isnot to list the timing files. For more information aboutthe command channel. refer to the SmartModel LibraryUser’s Manual.Maps all model signal strengths to “strong” for alloutput events that have resistive strength. The default isto use resistive strength to reflect the true state of theSWIFT pin.Indicates that the historic style is to be used fortranscribing messages. The historic style messagecontains references only to timing version names anddoes not specify any time units. The default is thatmessages contain references to both timing versionnames and model names. Timing values are innanoseconds (ns).Disables mapping of SmartModel Library signalstrengths to “strong” strength, even if a historic modelmodel.v file (vshell) is detected. Use this switch if youwant your historic-mode design to use true resistivestrengths. This switch only works with the SWIFTinterface.270 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys ModelsLMTV CommandsLMTV commands are predefined tasks that you place within your testbench or design.LMTV commands all begin with an $lm_ prefix. Some of them have historiccounterparts, which begin with an $lai_ prefix. You can use any or all commands ineither the SWIFT or the Historic SmartModel modes, except for the$lm_monitor_vec_map() command, which can be used only in SWIFT SmartModelmode.NoteThe $lai_ commands are provided to support older designs. Therefore, youdo not have to convert $lai_ commands to $lm_ commands. However, whenstarting a new design it is best to use the $lm_ commands and not the $lai_commands.Here is a list of the LMTV interface commands:● “$lm_command() or $lai_command()” on page 272● “$lm_dump_file() or $lai_dump_file()” on page 273● “$lm_help()” on page 274● “$lm_load_file() or $lai_load_file()” on page 275● “$lm_monitor_enable() or $lai_enable_monitor()” on page 276● “$lm_monitor_disable() or $lai_disable_monitor()” on page 276● “$lm_monitor_vec_map() and $lm_monitor_vec_unmap()” on page 278● “$lm_status() or $lai_status()” on page 280October 6, 2003 Synopsys, Inc. 271

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_command() or $lai_command()These commands provide access to the SWIFT command channel. You can use them tosend a command to the session or to a model instance.Syntax$lm_command ( “session_cmmd_string” );$lm_command ( inst_path, “model_cmmd_string” );$lai_command ( “session_cmmd_string” );$lai_command ( inst_path, “model_cmmd_string” );Argumentssession_cmmd_stringinst_pathmodel_cmmd_stringThe SWIFT interface command to be sent to thesession.The path name to the SmartModel instance to send thecommand to. Used only with model commands.The SWIFT interface command to be sent to the modelinstance.For more information about the SWIFT command channel, refer to “The SWIFTCommand Channel” on page 21.ExamplesThe following example sends the ReportStatus command to the instance “U1”, causingit to generate a message reporting its configuration status.% $lm_command ( "U1", "ReportStatus" );The following example sends the TraceTimeFile off command to the session, causing itto stop issuing trace messages. Note that the absence of an instance name identifies thecommand as session-specific.% $lm_command ( "TraceTimeFile off" )272 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys Models$lm_dump_file() or $lai_dump_file()Use these commands to dump the memory contents of the instance inst_path into the filefilename. This works only for memory models. If the specified file already exists, it isoverwritten. Using this command eliminates the read cycles required to verify thesuccess of a test.You can reload the dumped file into a memory model using the $lm_load_file()command. The format of the dumped file is the same as the Synopsys memory imagefile format required by a memory model at initialization.Syntax$lm_dump_file ( inst_path, “filename” [,“file_type”] );$lai_dump_file ( inst_path, “filename” [,”file_type”] );Argumentsinst_pathfilenamefile_typeThe path name to the SmartModel instance whosememory information is to be dumped.The path name to the file that is to receive the dumpedmemory information from the model instance.The type of configuration file to be dumped. The onlyallowed value is MEMORY, which is also the default.This argument is provided for compatibility with thehistoric environment.October 6, 2003 Synopsys, Inc. 273

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_help()Use this command to display the syntax for all of the SWIFT interface commands.Syntax$lm_help();ExamplesThe following example shows the results of issuing the command $lm_help.C2 > $lm_help;LMTV commands:lm_command( "session_command" ): execute a session command.lm_command( inst_path, "model_command" ):execute a model command.lm_dump_file( inst_path, "file_name", ["file_type"] ):dump memory into file.lm_load_file( inst_path, ["file_name", "file_type"] ):load file of programmable device or memory.lm_monitor_enable( inst_path [, "win_element" [,...]] ):enable window Monitor.lm_monitor_disable( inst_path [, "win_element" [,...]] ):disable window Monitorlm_monitor_vec_map( var_name, inst_path, "win_element" [, index]):map window to a variable for monitoring.lm_monitor_vec_unmap( [var_name,] inst_path ):unmap window to stop monitoring.lm_status( inst_path ): dump instance status.Commands compatible with old release :lai_enable_monitor( "inst_path", [win_element],... ):enable window Monitor.lai_disable_monitor( "inst_path", [win_element],... ):disable window Monitor.lai_dump_file( "inst_path", "file_name", "file_type" ):dump memory into file.lai_load_file( "inst_path", "file_name", "file_type" ):load file of programmable device or memory.lai_status( "inst_path" ): dump instance data.274 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys Models$lm_load_file() or $lai_load_file()Use these commands to load the memory contents of the file filename into the instanceinst_path, which can be either a programmable device or a memory model. Using thesecommands eliminates the write cycles required to set up the contents of the model.The load_file operation causes the selected model to reset its internal state to simulationstartup conditions and then read the specified file. After the file is read, the model isevaluated as a function of the new internal state and the current inputs and outputs arescheduled with zero delay. After this initial evaluation phase, the model behaves as itwould normally.You can load a model with any file type that would normally be accepted by the modelat initialization. Additionally, the new configuration file you load is used for thespecified model instance after any subsequent command to reset or reinitialize.Syntax$lm_load_file ( inst_path [, “filename”, “file_type”] );$lai_load_file ( inst_path [, “filename”, “file_type”] );Argumentsinst_pathfilenamefile_typeThe path name to the SmartModel instance into whichthe contents of filename is to be loaded.The path name to the configuration file that is to beloaded for the model instance specified by inst_path.The default is to use a path name defined with thedefparam statement in the design.The type of file to be loaded. Allowed values areMEMORY, JEDEC, PCL, and SCF. The default is touse the file type of the file defined with the defparamstatement in the design.October 6, 2003 Synopsys, Inc. 275

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_monitor_enable() or $lai_enable_monitor()$lm_monitor_disable() or $lai_disable_monitor()Use these commands to enable or disable SmartModel Windows for one or morewindow elements of a model instance specified by inst_path. The SmartModelWindows feature allows you to view and change the contents of a model's internalregisters through predefined windows, which usually reflect the model's internal state.After enabling SmartModel Windows, you can read from the register using anappropriate Verilog command or by adding the path name to the list of signals beingtraced. If you attempt to read from an internal register without enabling SmartModelWindows the window content is not read.The $lm_monitor_enable() and $lm_monitor_disable() commands are provided forcompatibility with the historic environment. You cannot access arrays of registers, as inmemory window elements, using these commands.NoteAccessing internal states is memory-intensive, so you may notice someperformance degradation when SmartModel Windows is enabled.Syntax$lm_monitor_enable ( inst_path [, “window_element” [,...]] );$lm_monitor_disable ( inst_path [, “window_element” [,...]] );$lai_enable_monitor ( inst_path [, “window_element” [,...]] );$lai_disable_monitor ( inst_path [, “window_element” [,...]] );Argumentsinst_pathwindow_elementThe path name to the SmartModel instance for whichSmartModel Windows is to be enabled.The name of the internal register to read. This can be asingle value or a list. The default is to read all internalregisters of the instance.276 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys ModelsExamplesThe following example enables SmartModel Windows for all windows in instance“U1”, then reads from the predefined window element IENA. Notice that you mustenable SmartModel Windows before attempting to read from the window element.// somewhere in the testbench ...// enable access to all windows in instance U1$lm_monitor_enable( U1 );// display contents of window element IENA$display("Value of register IENA is %h", $IENA);The following example disables the window explicitly for the register IENA.% $lm_monitor_disable( U1, "IENA" );The following example disables all windows in instance U1.% $lm_monitor_disable( U1 );The following example does not read the register IENA, because SmartModel Windowswas not enabled.// somewhere in the testbench ...$display("Value of register IENA is %h", $IENA);October 6, 2003 Synopsys, Inc. 277

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_monitor_vec_map() and$lm_monitor_vec_unmap()Use these commands to enable or disable direct mapping between the user-definedvariable var_name and a model instance's internal register window_element. Thismapping allows you to read from, write to, or trace the internal register through youruser-defined variable. You must define this variable with a width corresponding to thatof the predefined window somewhere in the design hierarchy (typically in the testbench)before using these commands. Note that these commands only work in SWIFTSmartModel mode.Using $lm_monitor_vec_map(), you can access arrays of registers, which is useful foraddressing specific memory locations, as in the memory window elements feature. Inaddition, $lm_monitor_vec_map() allows dynamic window creation.Syntax$lm_monitor_vec_map (var_name, inst_path, “window_element” [,index]);$lm_monitor_vec_unmap ([var_name,] inst_path);Argumentsvar_nameinst_pathwindow_elementindexThe name of a user-defined variable to map towindow_element. The variable must be alreadydefined somewhere in the design hierarchy. Thedefault for $lm_monitor_vec_unmap() is to unmap allmapped variables for that instance.The path name to the SmartModel instance whoseinternal register is to be mapped to the user-definedvariable var_name.The name of the internal register to be mapped tovar_name. Can be part of an array.The index of the array, if the window element is amemory window. The default is 0.ExamplesThe following example defines three variables and maps them to specific memorylocations in the memory array UMEM for memory model instance “U1”. Note thatthese tasks cannot be performed using $lm_monitor_enable(). Although the examplefeatures an array of registers, the tasks are equally useful for scalar windows, where youcan omit the index option or set it to 0.// Assume a 4Kx8 memory model, on a controller board.278 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix A: Using LMTV with Synopsys Models// Such a model would typically have one window called UMEM.// This window is a 4K deep array of 8 bit registers. In// particular, the user is interested in these 3 locations:// Interrupt service routine, LOW ADDRESS: 100// Interrupt service routine, HIGH ADDRESS: 101// Control store : 200// that are significant to the design.reg [7:0] ISR_LOW; // variable to map to location 100reg [7:0] ISR_HIGH; // variable to map to location 101reg [7:0] CONTROL; // variable to map to location 200// enable monitoring of these variables$lm_monitor_vec_map( ISR_LOW, U1, "UMEM", 100 );$lm_monitor_vec_map( ISR_HIGH, U1, "UMEM", 101 );$lm_monitor_vec_map( CONTROL, U1, "UMEM", 200 );// ... at this time, you can read, write, or trace these// variables. For example, assign the address of the interrupt// service routine to be 0x5000ISR_LOW = 0x00 ;ISR_HIGH = 0x50 ;// or the same assignment can be done as follows:define ISR {ISR_HIGH,ISR_LOW}ISR = 16h5000 ;// this one statement will access two different// and independent memory locations at once.// later in the simulation, you can disable monitoring// for the ‘CONTROL' register:$lm_monitor_vec_unmap( CONTROL, U1 );// or you can disable monitoring of all windows in that instance:$lm_monitor_vec_unmap( U1 );October 6, 2003 Synopsys, Inc. 279

Appendix A: Using LMTV with Synopsys ModelsSimulator Configuration Guide$lm_status() or $lai_status()Use these commands to report the current status of the model instance inst_path. Thereport includes the names and values of internal windows.Syntax$lm_status (inst_path)$lai_status (inst_path);Argumentsinst_pathThe path name to the SmartModel instance whosestatus is to be reported.ExamplesThe following example shows the output of the $lm_status() command for modelinstance “U1”.C1 > $lm_status(U1);Note: Model template: memVersion: not availableInstanceName: DESIGN.U1TimingVersion: MEM-0DelayRange: MAXMemoryFile: memory.1Timing Constraints: OnSmartModel Instance DESIGN.U1(mem:MEM-0), at time 1000.0 nsNote: SmartModel Windows Description:UMEM[2048] "2K x 8 Static RAM":SmartModel Windows not enabled for this model.SmartModel Instance DESIGN.U1(mem:MEM-0), at time 1000.0 ns280 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsBUsing Custom Memory ModelsThe DesignWare Memory Model technology software package supports custommemory models. These custom models are produced in Verilog or VHDL, and do notuse the SWIFT interface, but do require simulator-specific PLI/CLI/FLI code that mustbe bound into the supported simulator executable. Table 37 lists the simulators thatsupport custom memory models:Table 37: Simulators That Support Custom Memory ModelsVerilog SimulatorsVCSNC-VerilogMTI VerilogVHDL SimulatorsSciroccoMTI VHDLNC-VHDLSee the following sections for information on using custom memory models:● “Configuring Custom Memory Models” on page 282● “Controlling Messages” on page 283● “Instantiating Custom Memory Models” on page 285● “Using Custom Memory Models with VCS” on page 286● “Using Custom Memory Models with NC-Verilog” on page 289● “Using Custom Memory Models with MTI Verilog” on page 290● “Using Custom Memory Models with Scirocco” on page 292● “Using Custom Memory Models with MTI VHDL” on page 294● “Using Custom Memory Models with NC-VHDL” on page 296● “Using Custom Memory Models with VERA” on page 299October 6, 2003 Synopsys, Inc. 281

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideConfiguring Custom Memory ModelsRegardless of which simulator you are using, you must configure your custom memorymodels by defining the required parameters or attributes shown in Table 38 for eachmodel instance in your design. You configure custom memory models when youinstantiate them in your design using these generics or parameters.Table 38: Custom Memory Model Generic/Parameter DescriptionsName Data Type Descriptionmodel_idmodel_aliasIntegerStringEither the model_id or model_alias generic or parameterspecifies a unique user handle for a specified model instance.This user handle is used to address a memory model usingtestbench commands.Note: You do not need to assign all custom memory modelinstances a model_id or model_alias, but only those instanceson which you will use the testbench interface. However, eachmodel with a model_id or model_alias must be assigned aunique handle.memoryfile String Specifies the file name of the memory image file to preloadduring model initialization. If memoryfile is set to a nullstring (memoryfile = “”), memory image preloading duringinitialization is disabled. Supported file formats areSmartModel Memory Image, Motorola S-Record, Intel Hex,and Verilog $readmemh. Memory models can also be loadedusing the mem_load command.default_data String Specifies the default data returned from all uninitializedmemory addresses.Note: Models in non-volatile memory classes may not havetheir Default Memory Value set to anything except all ones.Any other setting is ignored.message_level Integer Specifies the type or types of messages returned by themodel. For a detailed description of message types, refer to“Controlling Messages” on page 283.AttentionThe spelling, case (upper/lower), and argument types of generics andparameters used by custom memory models are not always the same asthose used by standard binary DWMM models. Be sure to follow theappropriate conventions for your model.282 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsVHDL Interface CodeThe VHDL interface code is contained in the following files:slm_hdlc.vhd Simulator-specific HDL-to-C interface code.mempro_pkg.vhd Module containing the VHDL implementation of thetestbench interface.These files are located in the $LMC_HOME/sim/simulator/src directory.Verilog Routines and Interface CodeThese files define the PLI routines and interface commands for Verilog simulators:slm_pli.oPLI routines. This file is located in the$LMC_HOME/lib/platform.lib directory.mempro_pkg.vControlling MessagesVerilog testbench task definitions for interface commands.This file is located in the $LMC_HOME/sim/pli/src directory.The messages used by custom memory models are grouped into categories that you canenable or disable individually for each model instance. Several message categoriesapply to all models, and you can define additional categories for specific models ormodel types. These are the general message categories:●●●●●●Fatal messages are always enabled. When a fatal error is detected, the simulationreports the message, then stops immediately. For example, referencing an unknownmemory model instance handle causes a fatal error.Error messages apply to incorrect situations from which the model can recover,allowing simulation to continue. For example, a custom memory model generatesan error message when it receives a command that would put it in an illegal state.Warning messages apply to situations that users may want to check, but are notnecessarily wrong. For example, custom memory models generate warningmessages when significant address bits are ignored.Info messages tell you of the status or behavior of the model. For example, when acustom memory model is initialized from a file, an info message is generated.Timing messages report timing constraint violations, such as occur with setup orpulse-width violations.X-handling messages report instances in which unknowns are sampled on inputports when valid data was expected.October 6, 2003 Synopsys, Inc. 283

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideControlling Message OutputThere are three ways to control messaging for custom memory models:1. Specify Message Settings when you specify message categories (except Fatal).2. Use the message_level generic or parameter.3. Use a command stream or testbench command.By default, custom memory models display all the general message categories (Fatal,Error, Warning, Info, Timing, and X-handling). If you set a generic or parameter for amodel instance, that setting overrides the default behavior. In turn, if the commandstream or testbench interface is used, it overrides the generic or parameter value.Message Level ConstantsCustom memory models provide constants for setting message levels on eachinstantiated model. The constants described in Table 39 are defined in mempro_pkg.v(for Verilog simulators) and mempro_pkg.vhd (for VHDL simulators).You can combine these constants to get any combination of messages. The followingVerilog and VHDL code fragments define a model instantiation having timing,X-handling, and warning (as well as fatal) messages enabled.Verilogbank1.message_level = `SLM_XHANDLING | `SLM_TIMING | `SLM_WARNING,VHDLTable 39: Custom Memory Model Message ConstantsConstantValue a DescriptionSLM_ERROR 1 Fatal and error messages generated.SLM_WARNING 2 Fatal and warning messages generated.SLM_TIMING 4 Fatal and timing messages generated.SLM_XHANDLING 8 Fatal and X-handling messages generated.SLM_INFO 16 Fatal messages generated. Note: Using this bit can addlarge amounts of memory cycle information to thetranscript, considerably slowing simulation.SLM_ALL_MSGS 2 32 −1 All message types generated.SLM_NO_MSGS 0 Only fatal messages generated.a. Note that bits 5 through 31 are unused but reserved.message_level => (SLM_TIMING + SLM_XHANDLING + SLM_WARNING),284 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsInstantiating Custom Memory ModelsYou instantiate custom memory models just as you would any other HDL models, asshown in the following examples using DRAM.Verilog Instantiationdram1x64 bank1( .ras ( rasr ),.ucas ( ucasr ),.lcas ( lcasr ),.we ( wer ),.oe ( oer ),.a ( adrr ),.dq ( dataw ));defparam bank1.model_id = 10,bank1.memoryfile = "dram.dat",bank1.message_level = `SLM_XHANDLING | `SLM_TIMING | `SLM_WARNING,bank1.default_data = 64'hxxx;VHDL InstantiationU1 : dram1x64generic map ( model_id => 10,memoryfile => "dram.dat",message_level => (SLM_TIMING + SLM_XHANDLING + SLM_WARNING),default_data => "XXXX");port map( a => adrw,dq=> dataw,ras=> rasw,lcas=> lcasw,ucas=> ucasw,we=> wew,oe => oew );October 6, 2003 Synopsys, Inc. 285

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideUsing Custom Memory Models with VCSTo use custom memory models with VCS, use the following procedures for Verilog andC testbenches. VCS links external PLI routines during compilation of your design. Youdo not need to rebuild the VCS simulator.Using Custom Memory Models with VCS and VerilogTestbenches1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. If you are using HDL testbench interface commands in your design, add thefollowing line to your Verilog testbench — otherwise, skip to step 3.`include "mempro_pkg.v"For more information on using the HDL testbench interface, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.3. Instantiate your custom memory models in your design. Define ports andparameters as required. For details, see “Instantiating Custom Memory Models” onpage 285.4. Invoke VCS to compile your design, as shown in the following examples:❍❍Solaris:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \-P $LMC_HOME/sim/pli/src/slm_pli.tab \+incdir+$LMC_HOME/sim/pli/srcIf you are using the MemScope Dynamic Data Exchange (DDX) feature:% vcs Verilog_modules custom_model_files \+vcs+lic+wait \-Xstrict=0x01 -syslib “-lpthread” \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \-P $LMC_HOME/sim/pli/src/slm_pli.tab \+incdir+$LMC_HOME/sim/pli/srcHP-UX:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/hp700.lib/slm_pli.o \-P $LMC_HOME/sim/pli/src/slm_pli.tab \+incdir+$LMC_HOME/sim/pli/src \286 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory Models❍Linux:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/x86_linux.lib/slm_pli.o \-P $LMC_HOME/sim/pli/src/slm_pli.tab \+incdir+$LMC_HOME/sim/pli/src \-LDFLAGS -rdynamic5. Invoke VCS and simulate your design:% simvUsing Custom Memory Models with VCS and CTestbenchesIf you are using DWMM C testbench interface functions in your design, use thefollowing procedure.1. Develop a C testbench with your own routines that call the C interface functions.For more information on using the C testbench interface, refer to the “SystemCTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.2. Add the following line to your C testbench.#include "mempro_c_tb.h"3. Make a local copy of slm_pli.tab by copying from$LMC_HOME/sim/pli/src/slm_pli.tab and adding the following line for each Croutine you have developed:$your_task_name call=your_func_name4. Instantiate your custom memory models in your Verilog design. Define ports andparameters as required. For information on parameters used with custom memorymodels, see “Instantiating Custom Memory Models” on page 285.5. Add calls to the Verilog tasks that correspond with your SystemC routines, fromyour local slm_pli.tab file, to your Verilog design. For example:$your_task_name();6. Invoke VCS to compile your design:❍Solaris:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/srcOctober 6, 2003 Synopsys, Inc. 287

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide❍❍If you are using the MemScope Dynamic Data Exchange (DDX) feature:% vcs Verilog_modules custom_model_files \-Xstrict=0x01 -syslib “-lpthread” \$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/srcHP-UX:Linux:% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/hp700.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/src \% vcs Verilog_modules custom_model_files \$LMC_HOME/lib/x86_linux.lib/slm_pli.o \-P local_slm_pli.tab your_testbench.c \-CFLAGS “-I$LMC_HOME/include” \+incdir+$LMC_HOME/sim/pli/src \-LDFLAGS -rdynamic7. Invoke VCS and simulate your design:% simvVCS Custom Memory Model ExplanationTable 40 lists and explains each line in the invocation examples above.Table 40: VCS Custom Memory Model ExplanationLine Reference$VCS_HOME/bin/vcscustom_model.v custom_model_tb.vDescriptionPath to the file that starts the VCS simulator,followed by the specified model andtestbench Verilog files.-P $LMC_HOME/sim/pli/src/slm_pli.tab Specifies the PLI table entry file.$LMC_HOME/lib/sun4Solaris.lib/slm_pli.o-Mupdate-LDFLAGS switchesSpecifies the platform-specific PLI objectfile.This specifies incremental compilation,which causes VCS to compile only themodules that have changed since the last run.Additional platform-specific switches thatmay be needed.288 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsUsing Custom Memory Models withNC-VerilogCustom memory models work with NC-Verilog using a PLI application called LMTVthat is delivered in the form of a swiftpli shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.3. Instantiate your custom memory models in your design. Define ports andparameters as required. For information on parameters used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.4. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.5. Invoke the NC-Verilog simulator to compile and simulate your design as shown inthe example below:% ncverilog testbench Verilog_modules custom_model_files \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w6. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.❍❍Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.varOctober 6, 2003 Synopsys, Inc. 289

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide7. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v Verilog_modules custom_model_files \-incdir $LMC_HOME/sim/pli/src% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchUsing Custom Memory Models with MTIVerilogCustom memory models work with MTI Verilog (ModelSim) using a PLI applicationcalled LMTV that is delivered in the form of a swiftpli_mti shared library in$LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:1. Make sure MTI Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in the following example:% vlib work% vmap work workThis step also produces a modelsim.ini file.3. Edit the modelsim.ini file to add a resolution statement as shown in the followingexample:Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using SmartModels with ModelSim Verilog” onpage 61).4. To include DWMM testbench interface commands in your design, add the followingline to your testbench:`include "mempro_pkg.v"For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.290 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory Models5. Instantiate your custom memory models in your design. Define ports andparameters as required. For details, see “Instantiating Custom Memory Models” onpage 285. For information on message levels and message level constants, see“Controlling Messages” on page 283.6. Define the working directory that contains your testbench.% vlib work_dir7. Compile your code as shown in the following examples:% vlog -work work_dir testbench.v Verilog_modules custom_model_files\+incdir+$LMC_HOME/sim/pli/src8. Invoke the simulator as shown in the following examples:❍❍❍HP-UX:% vsim -pli $LMC_HOME/lib/hp700.lib/swiftpli_mti.sl \-c work_dir.testbenchSolaris:% vsim -pli $LMC_HOME/lib/sun4Solaris.lib/swiftpli_mti.so \-c work_dir.testbenchLinux:% vsim -pli $LMC_HOME/lib/x86_linux.lib/swiftpli_mti.so \-c work_dir.testbenchNoteIf you are also using SmartModels, FlexModels, or DesignWare MemoryModels in your design, you do not need to load the swiftpl_mti again, sincethe same library is used to enable all three types of models in MTI-Verilog.October 6, 2003 Synopsys, Inc. 291

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideUsing Custom Memory Models with SciroccoTo use Scirocco with custom memory models, follow this procedure.1. Make sure Scirocco is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 191.2. Add the Scirocco library path to your load library variable as shown in the followingexamples:❍❍❍HP-UX:% setenv SHLIB_PATH \$SYNOPSYS_SIM/hpux10/sim/lib:$SHLIB_PATHSolaris:Linux:% setenv LD_LIBRARY_PATH \$SYNOPSYS_SIM/sparcOS5/sim/lib:$LD_LIBRARY_PATH% % setenv LD_LIBRARY_PATH \$SYNOPSYS_SIM/linux/sim/lib:$LD_LIBRARY_PATH3. Add the Scirocco executable to your search path:% set path = ($SYNOPSYS_SIM/platform/sim/bin $path)where platform is hpux10 or sparcOS5.4. Create slm_lib and work directories:% mkdir ./slm_lib% mkdir ./work5. Create the logical to physical mapping for the slm_lib, work, and default libraries bymodifying your local .synopsys_vss.setup file to include the following lines:WORK > DEFAULTDEFAULT : ./workSLM_LIB : ./slm_lib6. Set your simulation timebase for the desired level of timing accuracy by modifyingyour .synopsys_vss.setup file to include a TIMEBASE entry, as shown in thefollowing example:TIMEBASE = PS292 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory Models7. Compile the DWMM VHDL files into your slm_lib library:NoteThese examples provide details for event-based simulation. For informationon cycle-based operation, see the Scirocco Reference Manual.% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/mempro_pkg.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.8. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% vhdlan mymem.vhd9. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.10. Instantiate your custom memory models in your design. Define ports and genericsas required. For details, see “Instantiating Custom Memory Models” on page 285.For information on message levels and message level constants, refer to“Controlling Messages” on page 283.11. Compile your testbench as shown in the following example% vhdlan testbench.vhd12. Invoke the Scirocco simulator as shown in the following examples:❍If you are using Scirocco 2001.10 or later:% scs testbench_configuration% scsim -vhpi slm_vhpi:foreignINITelab:cpipe❍ If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe testbench_configurationOctober 6, 2003 Synopsys, Inc. 293

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideUsing Custom Memory Models withMTI VHDLTo use custom memory models with MTI VHDL, follow this procedure:1. Make sure MTI VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 73.2. Append the shared library location to the library search path environment variablesetting.❍❍Solaris or Linux:% setenv LD_LIBRARY_PATH \$LMC_HOME/lib/platform.lib:$LD_LIBRARY_PATHwhere platform is sun4Solaris or x86_linuxHP-UX:% setenv SHLIB_PATH \$LMC_HOME/lib/hp700.lib:$SHLIB_PATH3. Create slm_lib and work directories:% vlib ./slm_lib% vlib ./work4. Create the logical to physical mapping for the slm_lib and work libraries:% vmap slm_lib ./slm_lib% vmap work ./workThis step also creates a modelsim.ini file in the current working directory.5. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100ps6. Compile the DWMM VHDL files into your slm_lib library:% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/mempro_pkg.vhd294 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory Models7. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% vcom -93 -work work mymem.vhd8. Add LIBRARY and USE statements for the slm_lib to your testbench code:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.9. Instantiate your custom memory models in your testbench. Define ports andgenerics as required. For information on generics used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.10. Compile your testbench into your work library as shown in the following example:% vcom -work work testbench.vhd11. Invoke the simulator on your testbench as shown in the following example:% vsim testbenchOctober 6, 2003 Synopsys, Inc. 295

Appendix B: Using Custom Memory ModelsSimulator Configuration GuideUsing Custom Memory Models withNC-VHDLAttentionFor best performance, use version 4.0 or later of NC-VHDL: this allows youto load multiple dynamic libraries containing C code. To use this means ofloading the DWMM routines, include the following option in the lineinvoking ncsim:ncsim -loadfmi libfmi_ml.so:slm_boot libfmi_ml.so (or .sl on hpux platforms) contains the library table andbootstrap function needed by the dynamic loader included in NC-VHDLversion 4.0 and above.This method eliminates the need to link libfmi_ar.a with your other externalC (foreign language) module to produce a single libfmi.so that incorporatesall foreign language modules in a single library.For more information about using the NC-VHDL with multiple dynamiclibraries, see your Cadence simulator documentation.To use custom memory models with NC-VHDL, follow this procedure:1. Make sure NC-VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 107.2. If you have built your own Foreign Model Interface (FMI) shared library (forexample, if you’re using VERA or Synopsys VMT models, or your own FMI code),perform this step. Otherwise, skip to step 3.NC-VHDL binds in only one shared FMI library at runtime. If your design usesFMI, you need to build a new FMI shared library that contains your library and theDWMM library. You can find a DWMM archive library here:❍❍HP-UX:$LMC_HOME/lib/hp700.lib/libfmi_ar.aSolaris:$LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.aYou must create a new archive that includes the DWMM archive, library table filedeclaration object file, and your archive. Detailed instructions for this process canbe found in the “Foreign Model Integration” chapter of the Affirma NC VHDLSimulator C Interface User Guide.296 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsYou must combine the contents of the DWMM library table file with your own FMIapplication library table, as shown in the following example:#include extern fmiModelTableT CpipeModelTable;extern fmiModelTableT myFMITable;fmiLibraryTableT fmiLibraryTable = {{"Cpipe", CpipeModelTable},{"myFMIlib", myFMITable},{0, 0}};Link the DWMM archive library with the new library table object file and any otherFMI application object files you wish to include, following the instructions in theCadence C Interface User Guide.The following examples show compiling the library table object files and linkingDWMM libfm_ar.a with the library table object file and the FMI application youdeveloped, shown in the examples as new_FMI_table.o and your_archive.a:❍❍HP-UX% /bin/cc -D_NO_PROTO -c +Z -I$CDS_VHDL/include new_FMI_table.c% /bin/ld -b -o libfmi.sl new_FMI_table.o your_archive.a \$LMC_HOME/lib/hp700.lib/libfmi_ar.aSolaris• For NC-VHDL version 4.0 and above:ncsim -loadfmi libfmi_ml.so:slm_boot Notelibfmi_ml.so is not compatible with versions of NC-VHDL earlier than 4.0.• For NC-VHDL versions before 4.0:% /opt/SUNWspro/bin/cc -c -KPIC -I$CDS_VHDL/include new_FMI_table.c% /opt/SUNWspro/bin/cc -G -o libfmi.so new_FMI_table.o \your_archive.a $LMC_HOME/lib/sun4Solaris.lib/libfmi_ar.a3. Create slm_lib and work directories:% mkdir ./slm_lib% mkdir ./workOctober 6, 2003 Synopsys, Inc. 297

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide4. Create the logical-to-physical mapping for the slm_lib and work libraries by addingthe following lines to your cds.lib file:define slm_lib ./slm_libdefine work ./work5. Compile the DWMM VHDL files into your slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhd% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd6. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% ncvhdl -w work mymem.vhd7. Add LIBRARY and USE statements for the slm_lib within your testbench code:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.8. Instantiate your custom memory models in your testbench. Define ports andgenerics as required. For information on generics, see “Instantiating CustomMemory Models” on page 285. For information on message levels and messagelevel constants, see “Controlling Messages” on page 283.9. Compile your testbench into your work library as shown in the following example:% ncvhdl -w work testbench.vhd10. Elaborate your design as shown in the following example:% ncelab testbench_configuration11. Invoke the NC-VHDL simulator as shown in the following example:% ncsim testbench_configuration298 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideAppendix B: Using Custom Memory ModelsUsing Custom Memory Models with VERA“Using VERA with DesignWare Memory Models” on page 223 describes how to useVERA with standard DWMM models. Custom memory models operate with VERA inmuch the same way as do standard DWMM models, so the information in that sectionapplies to custom memory models as well.Custom Memory Model VERA ClassesVERA implements a number of useful features of an object-oriented language. Thecustom DWMM-VERA interface provides a class that contains public method functionsso that a VERA testbench can access custom memory models. This class inherits thebase class LstModel features.LstModel is an abstract or virtual class and cannot be instantiated directly in VERAtestbenches. Only an instance of a MemPro class can be created in a VERA testbench.The commands used to control memory models are public methods of the MemProclass. You can send custom memory models commands from VERA only through aninstance of the MemPro class.October 6, 2003 Synopsys, Inc. 299

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide300 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexIndexSymbols$add_instance command 133, 134, 157$lai_command command 272$lai_disable_monitor command 276$lai_dump_file command 273$lai_enable_monitor command 276$lai_load_file command 275$lai_status command 280$lm_command command 272$lm_dump_file command 273$lm_help command 274$lm_load_file command 275$lm_loop_instance 100$lm_monitor_disable command 276$lm_monitor_enable command 276$lm_monitor_vec_map command 278$lm_monitor_vec_unmap command 278$lm_status command 280$lm_timing_information 101$lm_timing_measurements 102$lm_unknowns 103+ncaccess+rw switch 96, 257+vera_finish_on_end switch 214Aadd breakpoint command 142add bus command 143add lists command 141, 143add monitors command 141add primitive command 134add synonym command 143add traces command 141Admin tool 126AIXcompiling C files 28AMPLE_PATH environment variable 126Analysis toolsMentor Graphics 167rules to determine descriptors 168AttributesSmartModel 19, 29B-bit2bus switch 83, 246Breakpointssetting with SmartModels 142Bus symbolsSmartModel 128Ccds.lib file 92, 94, 96, 114, 250, 257, 289cds.lib path 111CDS_INST_DIR environment variable 90Check Shell Software utility 172Command ChannelSWIFT 137, 160Command interactionQuickSim II 137, 160Command lineswitches, QuickSim II 136, 159Commands$add_instance 133, 134, 157$lai_command 272$lai_disable_monitor 276$lai_dump_file 273$lai_enable_monitor 276$lai_load_file 275$lai_status 280$lm_command 272$lm_dump_file 273$lm_help 274$lm_load_file 275$lm_loop_instance 100$lm_monitor_disable 276$lm_monitor_enable 276$lm_monitor_vec_map 278$lm_monitor_vec_unmap 278$lm_status 280October 6, 2003 Synopsys, Inc. 301

IndexSimulator Configuration Guide$lm_timing_information 101$lm_timing_measurements 102$lm_unknowns 103add breakpoint 142add bus 143add lists 141, 143add monitors 141add primitive 134add synonym 143add traces 141command channel 21create_smartmodel_lib 194, 199, 258flexm_setup 25force 142lm_disable_timing_checks 121lm_enable_timing_checks 121lm_loop_instance 121lm_model 166, 169, 171, 172, 174, 176lm_model, syntax 185lm_pam_shortage 121lm_pattern_history 122lm_timing_measurements 121lm_unknowns 121lm_vconfig 105lmsi list 202lmsi logon 202lmsvg 105LMTV 267lmvc_template 56ncelab 92, 95, 97, 113, 257, 290ncshell 109, 115, 251ncsim 92, 95, 97, 110, 119, 257, 290ncverilog 97ncvhdl 110, 115, 251ncvlog 92, 95, 97, 257, 290nologvectors signal instance 182propagation 180reg_model 145, 169, 176scsg 262, 264scsim 200, 259signal instance 137, 160, 177, 182, 183,185simv 55, 217sm_entity 76, 79, 82, 246tmg_to_ts 169tmg_to_ts, syntax 188unknown handling 180vcom 78, 81, 84, 247VERA 214vhdlan 197, 293vlib 78, 83, 246vmap 83, 246vsim 78, 81, 84, 247COMP property 131, 156Compiling C filesAIX 28HP-UX 27Linux 29Solaris 27Component interface 169Component registration 145components.vhd file 200, 259C-only Command Modecompiling C files 27with FlexModels 26Constraint mode switch 136Conversionsshell software 174technology file 174Convertertmg_to_ts 169create_smartmodel_lib command 194,199, 258Custom memory modelscontrolling message output 284dynamic linking with PLI 290instantiating 285message level constants 284messages 283with MTI Verilog 290with MTI VHDL 294with NC-VHDL 296with Scirocco 292with VCS 286with VERA 299with Verilog simulators 283with VHDL simulators 283Custom symbols 144, 163mapping 146302 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexDDeclarations, variable 174DefaultData parameter 32Delay files 174DelayRange 23DelayRange parameter 30Delays, propagation 174Descriptionsfunctional 167, 169graphical 167, 169technology 169timing 169Descriptors, determining for hardwaremodels 168Design ArchitectSmartModel library menus to 126with SmartModels 126Design Architect menusbuilding designs with SmartModels 131,156levels 132system 132Design environment, MGC 167Designsbuilding, using menus 131, 156building, without menus 133, 157DesignWare Memory Modelsfunction-only operation 30instantiating 33messages 31PLI static linking 66with MTI Verilog 66with MTI VHDL 82with NC-Verilog 95with NC-VHDL 114with QuickSim II 151with Scirocco 199with SystemC 261with VCS 53with VERA 223Drive strengths 135, 158DWMM 151, 152Eentities.vhd file 200, 259Environment variablesAMPLE_PATH 126CDS_INST_DIR 90LD_LIBRARY_PATH 40, 41, 60, 74,90, 91, 108, 124LM_DIR 40, 60, 74LM_LIB 40, 60, 74LM_LICENSE_FILE 40, 60, 74, 90,108, 123, 192, 261LMC_SFI 55LMC_TIMEUNIT 110, 114, 119SHLIB_PATH 41, 60, 75, 91, 108, 124SNPSLMD_LICENSE_FILE 40, 60, 74,90, 108, 123, 192, 261SSI_LIB_FILES 213SYNOPSYS_SIM 192VCS_HOME 41VCS_LMC 55VCS_LMC_HM_ARCH 55VCS_SWIFT_NOTES 41Errorsmessages 139registration 172Evaluationhardware models in QuickSim II 179ExamplesFlexModel VHDL instantiation 45, 64,81, 94, 198FlexModels with VCS 48FFault simulationwith SmartModels 22Filescds.lib 92, 94, 96, 111, 114, 250, 257,289components.vhd 200, 259delay (.DLY) 174entities.vhd 200, 259October 6, 2003 Synopsys, Inc. 303

IndexSimulator Configuration Guideforce value (.FRC) 174hdl.var 92, 94, 96, 257, 289lmtv.o 268mapping, pin 146, 147model.vhd 64, 80, 93model_fx_comp.vhd 80model_fx_sim.vhd 64, 80, 93model_mx.v 67, 95, 96, 249, 256model_mx.vhd 83, 115, 246, 251model_mx_bus.v 54model_mx_bw.vhd 83, 247model_mx_comp.vhd 115, 251model_tst.vhd 64, 80, 93modelsim.ini 80ncshell 112ncsim 114pin_map 146, 147pin_map, example 148state tracking (.TRK) 174synopsys_vss.setup 197technology 169, 174, 185technology, types 174timing 171timing check (.TCK) 174variable declaration (.DCL) 174veriuser.c 268vsystem.ini 80FlexCFile 24flexm_setup 25, 27FlexModelattributes 19examples with VCS 48fault simulation 22FlexModel SWIFT parameters 23FlexModelId 23FlexModelsdynamic linking with PLI 63, 92example instantiations 109, 113PLI static linking 289using with MTI VHDL 79VHDL instantiation 109, 113with MTI-Verilog 63with NC-VHDL 110with Scirocco 196with VCS 44with VERA 207FlexModelSrc 24FlexTimingMode 23FMI library 110, 296Force command 142Force values file 174GGraphical descriptions 169HHardware model functional descriptionswith QuickSim II 169Hardware modelsdynamic linking with PLI 68, 97functional descriptions with QuickSim II167linking simulators 37linking with SFI 37loop mode 183modifying 176performance monitoring 180, 184propagation delays 174registering 169, 171registration 169rules for determining descriptors 168script for Scirocco 204shell timing 179timingmeasurement 182timing checks 174unknown propagation 181variable declarations 174with IKOS Voyager 37with MTI Verilog 68with MTI VHDL 84with NC-Verilog 97with QuickSim II 166, 177with Scirocco 201with Teradyne LASAR 37with VCS 55with VEDA Vulcan 38with ViewLogic Fusion 38304 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexhdl.var file 92, 94, 96, 257, 289HP-UXcompiling C files 27IIKOS Voyager 37with hardware models 37Indeterminate strength mapping 181Information, signal instance 183Installing 151InstantiatingDesignWare Memory Models 33InstantiationFlexModel VHDL 42, 45, 61, 64, 81, 91,94, 198Instructiontracing, execution 142Interfaceshardware model component 169JJEDECFile property 130, 154LLD_LIBRARY_PATH environmentvariable 40, 41, 60, 74, 90, 91,108, 124LibrariesFMI 110, 296model_pkg.inc 44, 64model_pkg.o 27model_pkg.vhd 80model_pkg.vr 213model_pkg.vrh 213model_user_pkg.vhd 80slm_lib 81, 83, 113, 114, 197, 246, 250slm_pli.o 27slm_pli_dyn 268SmartModel Library menus 126swiftpli 61, 63, 66, 91, 92, 94, 95, 289,290LIBRARY statement 81, 109, 113, 115,198, 251libsm 82, 245libswift 82, 245Linuxcompiling C files 29LM_DIR environment variable 40, 60, 74lm_disable_timing_checks command 121lm_enable_timing_checks command 121LM_LIB environment variable 40, 60, 74LM_LICENSE_FILE environmentvariable 40, 60, 74, 90, 108, 123,192, 261lm_loop_instance command 121lm_model command 166, 169, 171, 172,174, 176, 185lm_model symbol generation 173lm_pam_shortage command 121lm_pattern_history command 122lm_timing_measurements command 121lm_unknowns command 121lm_vconfig command 105LMC_COMMANDsetting SWIFT session commands 21LMC_HOME environment variable 40, 59,73, 89, 108, 123, 191, 261LMC_SFI environment variable 55LMC_TIMEUNIT environment variable110, 114, 119lmmsi logon command 202lmsi list command 202LMSI_DELAY_TYPE VHDL generic 203LMSI_LOG VHDL generic 203LMSI_TIMING_MEASUREMENTVHDL generic 203LMTVcommand reference 267command-line switches 270static linking with PLI 289lmvc_template command 56lmvsg command 105Location mapsvariables, Mentor Graphics 126October 6, 2003 Synopsys, Inc. 305

IndexSimulator Configuration GuideLogging test vectors 182Logic simulation 134, 158with SmartModels 134, 158Loop mode, with hardware models inQuickSim II 183MMappingindeterminate strength 181pin 147PIN_NAME 146pins, conditional 149unknowns 180Measurement, timing 182Memory image formats$readmemh 31MIF 31MemoryFile parameter 31MemoryFile property 129, 154MemPro modelsdynamic linking with PLI 97with NC-Verilog 97Mentor Graphicsanalysis tools 167design environment 167location map variables 126user tree management 125MessageLevel parameter 31Messagescustom memory models 283custom memory models, constants 284custom memory models, controlling 284DesignWare Memory Models 31SmartModel error 139SmartModel format 139SmartModel note 139SmartModel trace 139SmartModel warning 139MGC component interface 167MODEL property 130, 155model.vhd 64, 80model.vhd file 93model_fx_comp.vhd 80model_fx_sim.vhd 64, 80model_fx_sim.vhd file 93model_mx.v file 67, 95, 96, 249, 256model_mx.vhd file 83, 115, 246, 251model_mx_bus.v file 54model_mx_bw.vhd file 83, 247model_mx_comp.vdh file 115, 251model_pkg.o 27model_pkg.vhd 80model_tst.vhd 64, 80model_tst.vhd file 93model_user_pkg.vhd 80ModelAccessfor QuickSim II 164ModelAccess for QuickSim IIversion number 164ModelAlias parameter 30ModelConfig parameter 33ModelId parameter 29modelsim.ini file 80MTI Verilogsimulating using LMTV 61with custom memory models 290with DesignWare Memory Models 66with FlexModels 63with Hardware models 68MTI VHDLwith custom memory models 294with DesignWare Memory Models 82with FlexModels 79with hardware models 84with SmartModels 75306 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexNncshell command 109, 115, 251ncshell file 112ncsim command 110, 119ncsim file 114NC-Verilogsimulating with LMTV 91with DesignWare Memory Models 95with hardware models 97with MemPro models 97with SmartModels 91ncverilog command 97NC-VHDLwith custom memory models 296with DesignWare Memory Models 114with FlexModels 110with SmartModels 109ncvhdl command 110, 115, 251nologvectors signal instance command 182PParameterMessageLevel 31Parametersalso called attributes 19, 29DefaultData 32DelayRange 23, 30FlexCFile 24FlexModelId 23FlexModelSrc 24FlexTimingMode 23MemoryFile 31ModelAlias 30ModelConfig 33ModelId 29TimingVersion 23, 30PCLFile property 130, 154PIN property 130, 146, 155Pin symbols 128pin_map file 146, 147example 148PIN_NAME mapping 146PIN_NAME property 131, 146, 156PIN_NO property 131Pinsmapping 147mapping, conditional 149PINTYPE property 130, 155PKG property 131PLIdynamic linking with custom memorymodels 290dynamic linking with FlexModels 63dynamic linking with Hardware models97dynamic linking with MemPro models 97dynamic linking with SmartModels 61static linking with DesignWare MemoryModels 66static linking with FlexModels 289static linking with SmartModels 63PLIWizard 268propagation command 180PropertiesCOMP 131, 156editing 139, 162JEDECFile 130, 154MemoryFile 129, 154MODEL 130, 155, 167PCLFile 130, 154PIN 130, 146, 155PIN_NAME 131, 146, 156PIN_NO 131PINTYPE 130, 155PKG 131REF 131, 156SCFFile 154SWIFT 145, 163SWIFT_TEMPLATE 130, 155symbol 128symbol, required for simulation 130, 155TimingVersion 129, 153October 6, 2003 Synopsys, Inc. 307

IndexSimulator Configuration GuideQQuickSim IIchanging timing 139, 162command interaction 137, 160command line switches 136, 159component interface 167constraint checking 139, 162constraint, switch 136default timing 135, 158DesignWare Memory Models with 151installing SWIFT interface 125interactive commands 137, 160managing user trees 125model symbol properties 130, 155simulating logic models 177SmartModel windows with 141SWIFT interface 125-time_scale switch 136, 159timing,switch 136, 159with hardware models 166RReconfigurationmodels, for simulation 138, 161REF property 131, 156reg_model command 145, 169, 176Register elementscombining with SmartModels 143Registration 176component 145errors, dealing with 172hardware models 169logic models 169, 171models 169Registration tools, reference 185Related documents 11run_flex_examples_in_vcs.pl Script 53SSCFFile property 154Schematic captureadding SmartModel to schematic 127Schematic Editorcreating instances 133, 134, 157Sciroccohardware model utilities 202script for hardware models 204VHDL generics 202with custom memory models 292with DesignWare Memory Models 199with FlexModels 196with hardware models 201with SmartModels 193Scriptsrun_flex_examples_in_vcs.pl 53vcs_sg 53vsg 67, 83, 95, 246, 249, 256scsg command 262, 264scsim command 200, 259Selection, timing shell 179Session, ending the simulation 184SFIlinking hardware models 37Shell software conversions with hardwaremodels 174Shell, timingwith hardware models 179SHLIB_PATH environment variable 41,60, 75, 91, 108, 124signal instance command 137, 160, 177,182, 183, 185Simulation session, ending 184Simulationsfault 22reconfiguring models for 138, 161single-step 142Simulator integrationLeapfrog 296ModelSim 79ModelSim VHDL 294MTI VHDL 79V-System 5.0 79308 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexsimv command 55, 217slm_lib library 83, 114, 246, 250sm_entity command 76, 79, 82, 246SmartModel Librarydocumentation 11fault simulation 22message formats 139SmartModel windowshow they work 141tracing instruction execution 142with QuickSim II 141SmartModelsadding to schematic 127attributes, required 19changing program flow 144changing program flows 144creating instances in QuickSim 133, 157drive strengths 135, 158dynamic linking with PLI 61, 91editing properties 139, 162evaluation 179fault simulation 22functional descriptions in QuickSim II167graphical descriptions with QuickSim II167instantiating 20library menus, to Design Architect 126logic simulation 134, 158message format 139message formats 139pin and bus symbols 128PLI static linking 63, 92reconfiguring for simulation 138, 161renaming instances in QuickSIM 143signal levels 135, 158status checking 138, 161support levels 135, 158SWIFT usage notes for MGC users 127symbol properties used by SWIFT 129,153symbols, creating new 145, 163symbols, modifying 145, 163technology descriptions with QuickSimII 167timing constraint checks 139, 162trace messages 139using with SWIFT simulators 18warning messages 139with MTI VHDL 75with NC-Verilog 91with NC-VHDL 109with Scirocco 193with SystemC 261with VCS 42SNPSLMD_LICENSE_FILE environmentvariable 40, 60, 74, 90, 108, 123,192, 261Solariscompiling C files 27SSI_LIB_FILES environment variable 213State tracking 174Statementstechnology file 174Support levelsSmartModels 135, 158SWIFT 18SWIFT Command Channel 21, 137, 160SWIFT interfaceproperties 145, 163QuickSim II, installing 125symbol properties 128usage notes for MGC users 127SWIFT parameterswith DesignWare Memory Models 29with FlexModels 23with SmartModels 19SWIFT_TEMPLATE property 130, 155swiftpli 61, 63, 66, 91, 92, 94, 95, 289,290Switches+ncaccess+rw 96, 257+vera_finish_on_end 214-bit2bus 83, 246command line, QuickSim II 136, 159constraint mode 136time scale 136, 159timing mode 136, 159October 6, 2003 Synopsys, Inc. 309

IndexSimulator Configuration GuideSymbol propertiesrequired for simulation 130, 155Symbols 127, 152, 176alternate, selecting 134buses 128creation 169custom 144, 163editing 173pins 128properties 128registration 169rules for creating 173SmartModel, creating new 145, 163SmartModel, modifying 145, 163SYNOPSYS_SIM environment variable192synopsys_vss.setup file 197SystemCwith DesignWare Memory Models 261with SmartModels 261TTechnology descriptions 169Technology files 169, 174, 185conversions 174types 174Teradyne LASARwith hardware models 37Test vector logging 182Timescaleswitch with SmartModels 136, 159Timing checkswith hardware models 174Timing descriptions 169Timing files 171Timing modeschanging 139, 162default 135, 158switch 136, 159Timing shell selection 179TimingVersion 23TimingVersion parameter 30TimingVersion property 129, 153tmg_to_ts command 188tmg_to_ts converter 169ToolsAdmin 126analysis, Mentor Graphics 167flexm_setup 25, 27lm_model 166, 169, 171, 172, 174, 176lm_model, syntax 185reg_model 145, 169, 176registration, reference 185tmg_to_ts 169tmg_to_ts, syntax 188Tracinginstruction, execution 142Tracking, state 174Transcript, registration - checking 172Treesmanagement, Mentor Graphics 125Triggeringword, setting 142Typographical conventions 14UUnknown mappingwith hardware models 180Unknown propagationwith hardware models 181USE statement 81, 109, 113, 115, 198,251Using FlexModelswith C-only Command Mode 26with SWIFT simulators 26Utilitiescalled by lm_model command 169Check Shell Software 172lm_model 166, 169, 171, 172, 174, 176310 Synopsys, Inc. October 6, 2003

Simulator Configuration GuideIndexVVariableslocation map, Mentor Graphics 126vcom command 78, 81, 84, 247VCSFlexModel examples run script 51invoking on AIX 43invoking on HP-UX 42invoking on Linux 43invoking on Solaris 42with custom memory models 286with DesignWare Memory Models 53with FlexModels 44with hardware models 55with SmartModels 42with VERA 215VCS utilitieswith hardware models 58VCS_HOME environment variable 41VCS_LMC environment variable 55VCS_LMC_HM_ARCH environmentvariable 55vcs_sg script 53VCS_SWIFT_NOTES environmentvariable 41Vectors, test, logging 182VEDA Vulcanwith hardware models 38VERAcompiling source files 213compiling testbench 214testbench creation 210testbench example 211UDF interface 208with custom memory models 299with DesignWare Memory Models 223with FlexModels 207with FlexModels in testbench 211with VCS 215VERA command 214Veriloginclude pkgs 64slm_pli.o 27VHDL genericsLMSI_DELAY_TYPE 203LMSI_LOG 203LMSI_TIMING_MEASUREMENT 203with Scirocco 202vhdlan command 197, 293ViewLogic Fusionwith hardware models 38vlib command 78, 83, 246vmap command 83, 246vsg script 67, 83, 95, 246, 249, 256vsim command 78, 81, 84, 247V-System 79vsystem.ini file 80WWindowsSmartModel, tracing instructionexecution 142SmartModels, how they work 141SmartModels, with QuickSim II 141Word triggeringsetting 142WrappersSWIFT 93October 6, 2003 Synopsys, Inc. 311