ATxmega128A3U-MHR - E-LAB Computers

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Mnemonics Operands Description Operation Flags #ClocksSEV Set Two’s Complement Overflow V 1 V 1CLV Clear Two’s Complement Overflow V 0 V 1SET Set T in SREG T 1 T 1CLT Clear T in SREG T 0 T 1SEH Set Half Carry Flag in SREG H 1 H 1CLH Clear Half Carry Flag in SREG H 0 H 1MCU control instructionsBREAK Break (See specific descr. for BREAK) None 1NOP No Operation None 1SLEEP Sleep (see specific descr. for Sleep) None 1WDR Watchdog Reset (see specific descr. for WDR) None 1Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.2. One extra cycle must be added when accessing Internal SRAM.XMEGA A3U [DATASHEET]8386C–AVR–02/201364
35. Packaging information35.1 64APIN 1BePIN 1 IDENTIFIERE1ED1DC0°~7°LA1 A2 ACOMMON DIMENSIONS(Unit of measure = mm)Notes:1.This package conforms to JEDEC reference MS-026, Variation AEB.2. Dimensions D1 and E1 do not include mold protrusion. Allowableprotrusion is 0.25mm per side. Dimensions D1 and E1 are maximumplastic body size dimensions including mold mismatch.3. Lead coplanarity is 0.10mm maximum.SYMBOL MIN NOM MAX NOTEA – – 1.20A1 0.05 – 0.15A2 0.95 1.00 1.05D 15.75 16.00 16.25D1 13.90 14.00 14.10 Note 2E 15.75 16.00 16.25E1 13.90 14.00 14.10 Note 2B 0.30 – 0.45C 0.09 – 0.20L 0.45 – 0.75e0.80 TYP2325 Orchard ParkwaySan Jose, CA 95131TITLE DRAWING NO. REV.64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)64A2010-10-20CXMEGA A3U [DATASHEET]8386C–AVR–02/201365
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Features8/16-bit Atmel XMEGA A3U Mi
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3. OverviewThe Atmel AVR XMEGA is a
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4. ResourcesA comprehensive set of
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The arithmetic logic unit (ALU) sup
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Six of the 32 registers can be used
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7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63: Mnemonics Operands Description Oper
Page 67 and 68: 36. Electrical CharacteristicsAll t
Page 69 and 70: 36.1.3 Current consumptionTable 36-
Page 71 and 72: 36.1.4 Wake-up time from sleep mode
Page 77 and 78: Symbol Parameter Condition Min. Typ
Page 79 and 80: Table 36-21. Programming time.Symbo
Page 81 and 82: t CRV IH1V IL1t CLt CK36.1.14.6 Ext
Page 85 and 86: 36.1.15 SPI CharacteristicsFigure 3
Page 87 and 88: 36.1.16 Two-Wire Interface Characte
Page 89 and 90: 36.2 ATxmega128A3U36.2.1 Absolute M
Page 93 and 94: 36.2.4 Wake-up time from sleep mode
Page 95 and 96: 36.2.6 ADC characteristicsTable 36-
Page 101 and 102: Table 36-53. Programming time.Symbo
Page 103 and 104: t CRV IH1V IL1t CLt CK36.2.14.6 Ext
Page 107 and 108: 36.2.15 SPI CharacteristicsFigure 3
Page 109 and 110: 36.2.16 Two-Wire Interface Characte
Page 111 and 112: 36.3 ATxmega192A3U36.3.1 Absolute M
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36.3.4 Wake-up time from sleep mode
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36.3.6 ADC characteristicsTable 36-
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Symbol Parameter Condition Min. Typ
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Table 36-85. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.3.14.6 Ext
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36.3.15 SPI CharacteristicsFigure 3
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36.3.16 Two-Wire Interface Characte
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36.4 ATxmega256A3U36.4.1 Absolute M
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36.4.3 Current consumptionTable 36-
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36.4.4 Wake-up time from sleep mode
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36.4.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.4.14.6 Ext
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36.4.15 SPI CharacteristicsFigure 3
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36.4.16 Two-Wire Interface Characte
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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