ATxmega128A3U-MHR - E-LAB Computers

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3. OverviewThe Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers basedon the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA deviceachieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the systemdesigner to optimize power consumption versus processing speed.The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directlyconnected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many timesfaster than conventional single-accumulator or CISC based microcontrollers.The AVR XMEGA A3U devices provide the following features: in-system programmable flash with read-while-writecapabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmablemultilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); seven flexible, 16-bittimer/counters with compare and PWM channels; seven USARTs; two two-wire serial interfaces (TWIs); one full speedUSB 2.0 interface; three serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bitADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window mode;programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; andprogrammable brown-out detection.The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. Thedevices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chipdebug and programming.The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing theSRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-downmode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues torun, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, theexternal crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from theexternal crystal, combined with low power consumption. In extended standby mode, both the main oscillator and theasynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individualperipheral can optionally be stopped in active mode and idle sleep mode.Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVRmicrocontrollers.The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory canbe reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use anyinterface to download the application program to the flash memory. The boot loader software in the boot flash section willcontinue to run while the application flash section is updated, providing true read-while-write operation. By combining an8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family thatprovides a highly flexible and cost effective solution for many embedded applications.All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including Ccompilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.XMEGA A3U [DATASHEET]8386C–AVR–02/20134
3.1 Block DiagramFigure 3-1.XMEGA A3U block diagram.Digital functionAnalog functionProgramming, debug, testOscillator/Crystal/ClockGeneral Purpose I/OXTAL1XTAL2PR[0..1]PORT R (2)OscillatorCircuits/ClockGenerationReal TimeCounterWatchdogOscillatorDATA BUSWatchdogTimerPA[0..7]PORT A (8)ACAADCAEvent SystemControllerDMAControllerSRAMOscillatorControlSleepControllerPowerSupervisionPOR/BOD &RESETVCCGNDAREFABUS MatrixProg/DebugControllerPDIRESET/PDI_CLKPDI_DATAInt. Refs.TemprefAESOCDJTAGPORT BAREFBDESADCBCRCCPUInterruptControllerPB[0..7]/JTAGACBPORT B (8)DACBNVM ControllerFlashEEPROMUSARTF0TCF0PORT F (8)PF[0..7]IRCOMDATA BUSEVENT ROUTING NETWORKTCC0:1USARTC0:1SPICTWICTCD0:1USARTD0:1SPIDUSBTCE0:1USARTE0:1SPIETWIETo ClockGeneratorPORT C (8)PORT D (8)PORT E (8)TOSC1PC[0..7]PD[0..7]PE[0..7]TOSC2XMEGA A3U [DATASHEET]8386C–AVR–02/20135
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
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TXDnSSMOSIMISOSCKTransmitter Data f
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Table 32-3.Port C - alternate funct
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33. Peripheral Module Address MapTh
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34. Instruction Set SummaryMnemonic
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Mnemonics Operands Description Oper
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35. Packaging information35.1 64API
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36. Electrical CharacteristicsAll t
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36.1.3 Current consumptionTable 36-
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36.1.4 Wake-up time from sleep mode
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Symbol Parameter Condition Min. Typ
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Table 36-21. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.1.14.6 Ext
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36.1.15 SPI CharacteristicsFigure 3
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36.1.16 Two-Wire Interface Characte
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36.2 ATxmega128A3U36.2.1 Absolute M
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36.2.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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