ATxmega128A3U-MHR - E-LAB Computers

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28. ADC – 12-bit Analog to Digital Converter28.1 Features• Two Analog to Digital Converters (ADCs)• 12-bit resolution• Up to two million samples per second• Two inputs can be sampled simultaneously using ADC and 1x gain stage• Four inputs can be sampled within 1.5µs• Down to 2.5µs conversion time with 8-bit resolution• Down to 3.5µs conversion time with 12-bit resolution• Differential and single-ended input• Up to 16 single-ended inputs• 16x4 differential inputs without gain• 8x4 differential input with gain• Built-in differential gain stage• 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options• Single, continuous and scan conversion options• Four internal inputs• Internal temperature sensor• DAC output• V CC voltage divided by 10• 1.1V bandgap voltage• Four conversion channels with individual input control and result registers• Enable four parallel configurations and results• Internal and external reference options• Compare function for accurate monitoring of user defined thresholds• Optional event triggered conversion for accurate timing• Optional DMA transfer of conversion results• Optional interrupt/event on compare result28.2 OverviewThe ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to twomillion samples per second (msps). The input selection is flexible, and both single-ended and differential measurementscan be done. For differential measurements, an optional gain stage is available to increase the dynamic range. Inaddition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at alow system clock frequency. It also means that a new input can be sampled and a new ADC conversion started whileother ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay.The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control.The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with highdata throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC resultsdirectly to memory or peripherals when conversions are done.Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with theADC. The output from the DAC, V CC /10 and the bandgap voltage can also be measured by the ADC.The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software interventionrequired.XMEGA A3U [DATASHEET]8386C–AVR–02/201346
Figure 28-1. ADC overview.ADC0•ADC11ADC0•ADC7ADC4•ADC7Int. signalsADC0Internalsignals½x - 64xInternalsignalsV INPV INNCompareCH0 ResultCH1 ResultCH2 ResultCH3 ResultThreshold(Int Req)••ADC3Int. signalsInternal 1.00VInternal VCC/1.6VInternal VCC/2AREFAAREFBReferenceVoltageTwo inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and thegain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the application.The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µsfor 12-bit to 2.5µs for 8-bit result.ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation whenthe result is represented as a signed integer (signed 16-bit number).PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.XMEGA A3U [DATASHEET]8386C–AVR–02/201347
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 4 and 5: 3. OverviewThe Atmel AVR XMEGA is a
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63 and 64: Mnemonics Operands Description Oper
Page 65 and 66: 35. Packaging information35.1 64API
Page 67 and 68: 36. Electrical CharacteristicsAll t
Page 69 and 70: 36.1.3 Current consumptionTable 36-
Page 71 and 72: 36.1.4 Wake-up time from sleep mode
Page 77 and 78: Symbol Parameter Condition Min. Typ
Page 79 and 80: Table 36-21. Programming time.Symbo
Page 81 and 82: t CRV IH1V IL1t CLt CK36.1.14.6 Ext
Page 83 and 84: Symbol Parameter Condition Min. Typ
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Page 91 and 92: 36.2.3 Current consumptionTable 36-
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Page 95 and 96: 36.2.6 ADC characteristicsTable 36-
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Symbol Parameter Condition Min. Typ
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Table 36-53. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.2.14.6 Ext
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36.2.15 SPI CharacteristicsFigure 3
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36.2.16 Two-Wire Interface Characte
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36.3 ATxmega192A3U36.3.1 Absolute M
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36.3.3 Current consumptionTable 36-
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36.3.4 Wake-up time from sleep mode
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36.3.6 ADC characteristicsTable 36-
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Table 36-85. Programming time.Symbo
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36.4 ATxmega256A3U36.4.1 Absolute M
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36.4.3 Current consumptionTable 36-
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36.4.4 Wake-up time from sleep mode
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36.4.6 ADC characteristicsTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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