ATxmega128A3U-MHR - E-LAB Computers

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23. SPI – Serial Peripheral Interface23.1 Features• Three Identical SPI peripherals• Full-duplex, three-wire synchronous data transfer• Master or slave operation• Lsb first or msb first data transfer• Eight programmable bit rates• Interrupt flag at the end of transmission• Write collision flag to indicate data collision• Wake up from idle sleep mode• Double speed master mode23.2 OverviewThe Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. Itallows fast communication between an Atmel AVR XMEGA device and peripheral devices or between severalmicrocontrollers. The SPI supports full-duplex communication.A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID, and SPIE respectively.XMEGA A3U [DATASHEET]8386C–AVR–02/201342
24. USART24.1 Features• Seven identical USART peripherals• Full-duplex operation• Asynchronous or synchronous operation• Synchronous clock rates up to 1/2 of the device clock frequency• Asynchronous clock rates up to 1/8 of the device clock frequency• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits• Fractional baud rate generator• Can generate desired baud rate from any system clock frequency• No need for external oscillator with certain frequencies• Built-in error detection and correction schemes• Odd or even parity generation and parity check• Data overrun and framing error detection• Noise filtering includes false start bit detection and digital low-pass filter• Separate interrupts for• Transmit complete• Transmit data register empty• Receive complete• Multiprocessor communication mode• Addressing scheme to address a specific devices on a multidevice bus• Enable unaddressed devices to automatically ignore all frames• Master SPI mode• Double buffered operation• Operation up to 1/2 of the peripheral clock frequency• IRCOM module for IrDA compliant pulse modulation/demodulation24.2 OverviewThe universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serialcommunication module. The USART supports full-duplex communication and asynchronous and synchronous operation.The USART can be configured to operate in SPI master mode and used for SPI communication.Communication is frame based, and the frame format can be customized to support a wide range of standards. TheUSART is buffered in both directions, enabling continued data transmission without any delay between frames. Separateinterrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overfloware detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check canalso be enabled.The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud ratesfrom any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequencyto achieve a required baud rate. It also supports external clock input in synchronous slave operation.When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receivebuffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.The registers are used in both modes, but their functionality differs for some control settings.An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation anddemodulation for baud rates up to 115.2Kbps.PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripheralsare USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1 and USARTF0, respectively.XMEGA A3U [DATASHEET]8386C–AVR–02/201343
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 4 and 5: 3. OverviewThe Atmel AVR XMEGA is a
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 40 and 41: Multipacket transfer enables a data
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63 and 64: Mnemonics Operands Description Oper
Page 65 and 66: 35. Packaging information35.1 64API
Page 67 and 68: 36. Electrical CharacteristicsAll t
Page 69 and 70: 36.1.3 Current consumptionTable 36-
Page 71 and 72: 36.1.4 Wake-up time from sleep mode
Page 77 and 78: Symbol Parameter Condition Min. Typ
Page 79 and 80: Table 36-21. Programming time.Symbo
Page 81 and 82: t CRV IH1V IL1t CLt CK36.1.14.6 Ext
Page 83 and 84: Symbol Parameter Condition Min. Typ
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36.2.4 Wake-up time from sleep mode
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36.2.6 ADC characteristicsTable 36-
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Symbol Parameter Condition Min. Typ
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Table 36-53. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.2.14.6 Ext
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36.2.15 SPI CharacteristicsFigure 3
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36.2.16 Two-Wire Interface Characte
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36.3 ATxmega192A3U36.3.1 Absolute M
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36.3.3 Current consumptionTable 36-
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Table 36-85. Programming time.Symbo
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36.4 ATxmega256A3U36.4.1 Absolute M
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36.4.3 Current consumptionTable 36-
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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