ATxmega128A3U-MHR - E-LAB Computers

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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred asmultiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USBtransfers.For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle anda suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleepmode.PORTD has one USB. Notation of this is USB.XMEGA A3U [DATASHEET]8386C–AVR–02/201340
22. TWI – Two-Wire Interface22.1 Features• Two Identical two-wire interface peripherals• Bidirectional, two-wire communication interface• Phillips I 2 C compatible• System Management Bus (SMBus) compatible• Bus master and slave operation supported• Slave operation• Single bus master operation• Bus master in multi-master bus environment• Multi-master arbitration• Flexible slave address match functions• 7-bit and general call address recognition in hardware• 10-bit addressing supported• Address mask register for dual address match or address range masking• Optional software address recognition for unlimited number of addresses• Slave can operate in all sleep modes, including power-down• Slave address match can wake device from all sleep modes• 100kHz and 400kHz bus frequency support• Slew-rate limited output drivers• Input filter for bus noise and spike suppression• Support arbitration between start/repeated start and data bit (SMBus)• Slave arbitration allows support for address resolve protocol (ARP) (SMBus)22.2 OverviewThe two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I 2 C and System Management Bus(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing aslave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one orseveral masters that can take control of the bus. An arbitration process handles priority if more than one master tries totransmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.The TWI module supports master and slave functionality. The master and slave functionality are separated from eachother, and can be enabled and configured separately. The master module supports multi-master bus operation andarbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick commandand smart mode can be enabled to auto-trigger operations and reduce software complexity.The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing isalso supported. A dedicated address mask register can act as a second address match register or as a register foraddress range masking. The slave continues to operate in all sleep modes, including power-down mode. This enablesthe slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the addressmatching to let this be handled in software instead.The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,and clock hold on the bus are also detected and indicated in separate status flags available in both master and slavemodes.It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an externalTWI bus driver. This can be used for applications where the device operates from a different V CC voltage than used bythe TWI bus.PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.XMEGA A3U [DATASHEET]8386C–AVR–02/201341
Page 1 and 2: Features8/16-bit Atmel XMEGA A3U Mi
Page 4 and 5: 3. OverviewThe Atmel AVR XMEGA is a
Page 6 and 7: 4. ResourcesA comprehensive set of
Page 8 and 9: The arithmetic logic unit (ALU) sup
Page 10 and 11: Six of the 32 registers can be used
Page 12 and 13: 7.3.4 Production Signature RowThe p
Page 14 and 15: 7.8 Data Memory and Bus Arbitration
Page 16 and 17: 8. DMAC - Direct Memory Access Cont
Page 18 and 19: Figure 9-1.Event system overview an
Page 20 and 21: Figure 10-1. The clock system, cloc
Page 22 and 23: 11. Power Management and Sleep Mode
Page 24 and 25: 12. System Control and Reset12.1 Fe
Page 26 and 27: 13. WDT - Watchdog Timer13.1 Featur
Page 28 and 29: Program address(base address) Sourc
Page 30 and 31: 15.3.1 Push-pullFigure 15-1. I/O co
Page 32 and 33: 15.4 Input sensingInput sensing is
Page 34 and 35: Only Timer/Counter 0 has the split
Page 36 and 37: 18. AWeX - Advanced Waveform Extens
Page 38 and 39: 20. RTC - 16-bit Real-Time Counter2
Page 42 and 43: 23. SPI - Serial Peripheral Interfa
Page 44 and 45: 25. IRCOM - IR Communication Module
Page 46 and 47: 28. ADC - 12-bit Analog to Digital
Page 48 and 49: 29. DAC - 12-bit Digital to Analog
Page 50 and 51: 30. AC - Analog Comparator30.1 Feat
Page 52 and 53: 31. Programming and Debugging31.1 F
Page 54 and 55: TXDnSSMOSIMISOSCKTransmitter Data f
Page 56 and 57: Table 32-3.Port C - alternate funct
Page 58 and 59: 33. Peripheral Module Address MapTh
Page 60 and 61: 34. Instruction Set SummaryMnemonic
Page 63 and 64: Mnemonics Operands Description Oper
Page 65 and 66: 35. Packaging information35.1 64API
Page 67 and 68: 36. Electrical CharacteristicsAll t
Page 69 and 70: 36.1.3 Current consumptionTable 36-
Page 71 and 72: 36.1.4 Wake-up time from sleep mode
Page 77 and 78: Symbol Parameter Condition Min. Typ
Page 79 and 80: Table 36-21. Programming time.Symbo
Page 81 and 82: t CRV IH1V IL1t CLt CK36.1.14.6 Ext
Page 83 and 84: Symbol Parameter Condition Min. Typ
Page 85 and 86: 36.1.15 SPI CharacteristicsFigure 3
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36.2.3 Current consumptionTable 36-
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36.2.4 Wake-up time from sleep mode
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36.2.6 ADC characteristicsTable 36-
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Symbol Parameter Condition Min. Typ
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Table 36-53. Programming time.Symbo
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t CRV IH1V IL1t CLt CK36.2.14.6 Ext
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36.2.15 SPI CharacteristicsFigure 3
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36.2.16 Two-Wire Interface Characte
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36.3 ATxmega192A3U36.3.1 Absolute M
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Table 36-85. Programming time.Symbo
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36.4 ATxmega256A3U36.4.1 Absolute M
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Table 36-117.Programming time.Symbo
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37. Typical Characteristics37.1 ATx
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Figure 37-5. Active mode supply cur
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Figure 37-9. Idle mode supply curre
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Figure 37-13. Idle mode supply curr
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37.1.1.4 Power-save mode supply cur
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Figure 37-21. I/O pin pull-up resis
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Figure 37-25. I/O pin output voltag
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Figure 37-29. I/O pin output voltag
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Figure 37-33. I/O pin input thresho
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Figure 37-37. INL error vs. input c
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Figure 37-41. Gain error vs. V REF
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Figure 37-45. Offset error vs. V CC
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Figure 37-49. DNL error vs. V REF .
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Figure 37-53. Analog comparator hys
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Figure 37-57. Voltage scaler INL vs
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37.1.8 External Reset Characteristi
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Figure 37-65. Reset pin input thres
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37.1.10 Oscillator Characteristics3
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Figure 37-72. 2MHz internal oscilla
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Figure 37-76. 32MHz internal oscill
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37.2 ATxmega128A3U37.2.1 Current co
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Figure 37-88. Active mode supply cu
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Figure 37-104. I/O pin pull-up resi
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Figure 37-108. I/O pin output volta
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Figure 37-116. I/O pin input thresh
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Figure 37-120. INL error vs. input
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Figure 37-128. Offset error vs. V C
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Figure 37-132. DNL error vs. V REF
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Figure 37-136. Analog comparator hy
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Figure 37-140. Voltage scaler INL v
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Figure 37-148. Reset pin input thre
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Figure 37-159. 32MHz internal oscil
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Figure 37-171. Active mode supply c
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Figure 37-175. Idle mode supply cur
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Figure 37-254. Active mode supply c
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38. Errata38.1 ATxmega64A3U, ATxmeg
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39.3 8386A - 07/20111. Initial revi
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11. Power Management and Sleep Mode
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36.4 ATxmega256A3U . . . . . . . .
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